MAC7200 datasheet(779/976 Pages) FREESCALE

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Functional Description

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

701

32.13.1.1.1

General purpose Input/Output mode (GPIO) Mode

In GPIO mode, all input capture and output compare functions of the UC are disabled, the internal counter

(UCCNTn register) is cleared and disabled. All control bits remain accessible. In order to prepare the UC

for a new operation mode, writing to registers UCAn or UCBn stores the same value in registers A1/A2

or B1/B2, respectively.

MODE[0] bit selects between input (MODE[0] = 0) and output (MODE[0] = 1) modes.

It is required that when changing MODE[6:0], the application software goes to GPIO mode first in order

to reset the UC’s internal functions properly. Failure to do this could lead to invalid and unexpected output

compare or input capture results or the FLAGs being set incorrectly.

In GPIO input mode, the FLAG generation is determined according to EDPOL and EDSEL bits and the

input pin status can be determined by reading the UCIN bit.

In GPIO output mode, the Unified Channel is used as a single output port pin and the value of the EDPOL

bit is permanently transferred to the output flip-flop.

32.13.1.1.2

Single Action Input Capture (SAIC) Mode

In SAIC mode, when a triggering event occurs on the input pin, the value on the selected time base is

captured into register A2. At the same time, the FLAG bit is set to indicate that an input capture has

occurred. Register UCAn returns the value of register A2

The input capture is triggered by a rising, falling or either edges in the input pin, as configured by EDPOL

and EDSEL bits in UCCRn register.

Figure 32-14 shows how the Unified Channel can be used for input capture.

Figure 32-14. Single Action Input Capture example

32.13.1.1.3

Single Action Output Compare (SAOC) Mode

In SAOC mode a match value is loaded in register A2 and then transferred to register A1 to be compared

with the selected time base. When a match occurs, the EDSEL bit selects if the output flip-flop is toggled

or if the value in EDPOL is transferred to it. At the same time, the FLAG bit is set to indicate that the output

compare match has occurred. Writing to register UCAn stores the value in register A2 and reading to

selected counter bus

$000500

$001000

$001100

$001250

$001525

$0016A0

FLAG set event

(captured) value2

$xxxxxx

$001000

$001250

$0016A0

input signal1

Edge detect

Notes: 1. After input filter

2. UCAn <= A2

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