MAC7200 datasheet(783/976 Pages) FREESCALE

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Functional Description

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

705

in A2 and B1 registers. Transfers from B2 to B1 are then blocked until UCBn is read. After UCBn is read,

the transfer edges, which is the leading edge in the Figure 32-20 example.

Figure 32-20. A1 and B1 updates at UCAn and UCBn reads

32.13.1.1.6

Double Action Output Compare (DAOC) Mode

In the DAOC mode the leading and trailing edges of the variable pulse width output are generated by

matches occurring on comparators A and B, respectively.

When the DAOC mode is first selected (coming from GPIO mode) both comparators are disabled.

Comparators A and B are enabled by updating registers A1 and B1 respectively and remain enabled until

a match occurs on that comparator, when it is disabled again. In order to update registers A1 and B1, a

write to A2 and B2 must occur and the OUDISn bit must be cleared.

The output flip-flop is set to the value of EDPOL when a match occurs on comparator A and to the

complement of EDPOL when a match occurs on comparator B.

MODE[0] controls if the FLAG is set on both matches or just on the second match (see Table 32-16 for

details).

If subsequent enabled output compares occur on registers A1 and B1, pulses will continue to be generated,

regardless of the state of the FLAG bit.

At any time, the FORCMA and FORCMB bits allow the software to force the output flip-flop to the level

corresponding to a comparison event in comparator A or B, respectively. Note that the FLAG bit is not

affected by these forced operations.

NOTE

If both registers (A1 and B1) are loaded with the same value, the Unified

Channel behaves as if a single match on comparator B had occurred, i.e., the

output pin will be set to the complement of EDPOL bit and the FLAG bit is

set.

selected counter bus

$000500

$001000

$001100

$001250

$001525

$0016A0

A2(captured) value2

B2(captured) value

B1 value3

$xxxxxx

$001000

$001250

$0016A0

$xxxxxx

$001100

$001525

$xxxxxx

$001000

Input signal1

FLAG set event

EDPOL = 1

A1 value

$xxxxxx

$001000

$001250

Read UCAn

Read UCBn

$001250

Notes: 1. After input filter

2. UCAn = A2

3. UCBn = B1

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