MAC7200 datasheet(784/976 Pages) FREESCALE

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Functional Description

MAC7200 Microcontroller Family Reference Manual, Rev. 2

706

Freescale Semiconductor

Figure 32-21 and Figure 32-22 show how the Unified Channel can be used to generate a single output

pulse with FLAG bit being set on the second match or on both matches, respectively.

Figure 32-21. Double Action Output Compare with FLAG set on the second match

Figure 32-22. Double Action Output Compare with FLAG set on both matches

32.13.1.1.7

Pulse/Edge Accumulation (PEA) Mode

The PEA mode returns the time taken to detect a desired number of input events. MODE[0] bit selects

between continuos or single shot operation.

After writing to register A1, the internal counter is cleared on the first input event, ready to start counting

input events and the selected timebase is latched into register B2. On the match between the internal

counter and register A1, a counter bus capture is triggered to register A2 and B2. The data previously held

in register B2 is transferred to register B1 and the FLAG bit is set to indicate that an event has occurred.

The desired time interval can be determined subtracting register B1 from A2. Registers UCAn and UCBn

return the values in register A2 and B1, respectively.

selected counter bus

$000500

$001000

$001100

$001000

$001100

A1 value1

B1 value2 $xxxxxx $001100

$001100

$xxxxxx $001000

$001000

output flip-flop

MODE

A1 match

B1 match

Update to

A1 and B1

FLAG set event

A1 match

B1 match

Notes: 1. UCAn = A1

2. UCBn = B1

A2 = A1according to OUn bit

B2 = B1according to OUn bit

[0]= 0

selected counter bus

$000500

$001000

$001100

$001000

$001100

A1 value1

B1 value2 $xxxxxx $001100

$001100

$xxxxxx $001000

$001000

output flip-flop

A1 match

B1 match

Update to

A1 and B1

FLAG set event

A1 match

B1 match

Notes: 1. UCAn = A1

2. UCBn = B1

A2 = A1according to OUn bit

B2 = B1according to OUn bit

MODE[0]= 1

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