MAC7200 datasheet(780/976 Pages) FREESCALE

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Functional Description

MAC7200 Microcontroller Family Reference Manual, Rev. 2

702

Freescale Semiconductor

An output compare match can be simulated in software by setting the FORCMA bit in UCCRn register.

In this case, the FLAG bit is not set.

Figure 32-15 and Figure 32-16 show how the Unified Channel can be used to perform a single output

compare with EDPOL value being transferred to the output flip-flop and toggling the output flip-flop at

each match, respectively.

Figure 32-15. SAOC example with EDPOL value being transferred to the output flip-flop

Figure 32-16. SAOC example toggling the output flip-flop

32.13.1.1.4

Input Pulse Width Measurement (IPWM) Mode

The IPWM mode allows the measurement of the width of a positive or negative pulse by capturing the

leading edge on register B1 and the trailing edge on register A2. Successive captures are done on

consecutive edges of opposite polarity. The leading edge sensitivity (i.e., pulse polarity) is selected by

EDPOL bit in the UCCRn register. Registers UCAn and UCBn return the values in register A2 and B1,

respectively.

The capture function of register A2 remains disabled until the first leading edge triggers the first input

capture on register B2. When this leading edge is detected, the count value of the selected time base is

latched into register B2; the FLAG bit is not set. When the trailing edge is detected, the count value of the

selected time base is latched into register A2 and, at the same time, the FLAG bit is set and the content of

If subsequent input capture events occur while the corresponding FLAG bit is set, registers A2, B1 and A1

will be updated with the latest captured values and the FLAG will remain set. Registers UCAn and UCBn

return the value in registers A2 and B1, respectively.

selected counter bus

$000500

$001000

$001100

$001000

$001100

$001000

output flip-flop

Update to A1

value1 $xxxxxx $001000

FLAG set event

$001000

A1 match

Notes: 1. UCAn = A2

EDSEL = 0

EDPOL = 1

A2 = A1 according to OUn bit

selected counter bus

$000500

$001000

$001100

$001000

$001100

$001000

value1 $xxxxxx $001000

output flip-flop

Update to A1

FLAG set event

match

A1 match

match

$001000

Notes: 1. UCAn = A2

EDSEL = 1

EDPOL = x

A2 = A1 according to OUn bit

MAC7200 Datasheet(PDF) 780 Page - Freescale Semiconductor, Inc

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