MAC7200 datasheet(791/976 Pages) FREESCALE

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Functional Description

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

713

counter reaches the value one. Note that the internal counter values are within a range from one up to

MODE[0] bit selects internal clock source if set to zero or external, if set to one. When external clock is

selected the input channel pin is used as the channel clock source. The active edge of this clock is defined

by EDPOL and EDSEL bits in the UCCRn channel register.

When entering in MCB mode, if up counter is selected by MODE[2]=0, the internal counter starts counting

from its current value to up direction until A1 match occurs. On the next system clock cycle after A1 match

occurs the internal counter is set to one. If up/down counter is selected by setting MODE[2]=1, the counter

changes direction at A1 match and counts down until it reaches the value one. After it have reached one it

is set to count in up direction again. Register B1 is set to one at mode entering and cannot be changed while

this mode is selected. B1 register is used to generate a match in order to set the internal counter in up-count

direction if up/down mode is selected.

Note that differently from the MC mode, the MCB mode counts between one and A1 register value. The

counter cycle period is equal to A1 value in up counter mode. If in up/down counter mode the period is

defined by the expression: (2*A1)-2.

Figure 32-32 describes the counter cycle for several A1 values. Register A1 is loaded with A2 register

value at the cycle boundary. Thus any value written to A2 register within cycle (n) will be updated to A1

at the next cycle boundary and therefore will be used on cycle (n+1). The cycle boundary between cycle

(n) and cycle (n+1) is defined as the first system clock cycle of cycle (n+1). Note that the flags are

generated as soon as A1 match had occurred.

Figure 32-32. Modulus Counter Buffered (MCB) Up Count mode

Figure 32-33 describes the MCB in up/down counter mode. A1 register is updated at the cycle boundary.

If A2 is written in cycle (n), this new value will be used in cycle (n+1) for A1 match.

Flags are generated only at A1 match if MODE[1] is 0. If MODE[1] is set to 1 flags are also generated at

the cycle boundary.

UCCNTn

TIME

write to A2

match A1

write to A2

$000001

$000005

$000006

$000007

FLAG set event

A1 value

$000006

$000005

$000007

$000005

$000007

A2 value

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