MAC7200 datasheet(794/976 Pages) FREESCALE

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Functional Description

MAC7200 Microcontroller Family Reference Manual, Rev. 2

716

Freescale Semiconductor

Figure 32-36. OPWFM with immediate update

Figure 32-37. OPWFM with next period update

32.13.1.1.14 Pulse Width and Frequency Modulation Buffered (OPWFMB) Mode

This mode provides waveforms with variable duty cycle and frequency. The internal channel counter is

automatically selected as the time base when this mode is selected. A1 register indicates the duty cycle and

B1 register the frequency. Both A1 and B1 registers are double buffered to allow smooth signal generation

when changing the registers values on the fly. 0% and 100% duty cycles are supported.

In order to provide smooth and consistent channel operation this mode differs substantially from the

OPWFM mode. The main differences reside in the A1 and B1 registers update, on the delay from the A1

match to the output pin transition and on the range of the internal counter values which starts from 1 up to

B1 register value.

$001000

$000000

UCCNTn

Time

Match A1

output flip-flop

A1 value1

write to B2

$000200

B1 value

B2 value2

$000900

Match B1

Match A1

$001000

$000200

Match B1

$000900

write to A2/B2

Notes: 1. UCAn = A1

2. UCBn = B2

$000200

$001000

$000900

$000200

A2 = A1according to OUn bit

B2 = B1according to OUn bit

MODE[0]= 0

$001000

$000000

internal counter

Time

Match A1

output flip-flop

A1 value1

write to B2

$000200

B1 value

B2 value2

$000900

Match B1

Match A1

$xxxxxx

$001000

$000200

Match B1

$000900

$001000

write to A2/B2

Match A1

Match B1

$000900

$000200

$001000

$000200

$001000

$000200

$000900

Notes: 1. UCAn = A1

2. UCBn = B2

A2 = A1according to OUn bit

B2 = B1according to OUn bit

MODE[0]= 1

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