MAC7200 datasheet(796/976 Pages) FREESCALE

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Functional Description

MAC7200 Microcontroller Family Reference Manual, Rev. 2

718

Freescale Semiconductor

Figure 32-39. OPWFMB Mode with A1 = 0 (0% duty cycle)

Figure 32-40 describes the timing for the A1 and B1 registers load. The A1 and B1 load use the same signal

which is generated based on the selected counter reaching the value one, or UCCNTn = 1. This event is

defined as the cycle boundary. The load signal pulse has the duration of one system clock cycle and occurs

at the first system clock period of every counter cycle. If A2 and B2 are written within cycle (n) their values

are loaded into A1 and B1, respectively, at the first clock of cycle (n+1). The update disable bits OUDISn

can be used to control the update of these registers, thus allowing to delay the A1 and B1 registers update

for synchronization purposes.

During the load pulse A1 still holds its old value, which is updated only at the following system clock

cycle. During the A1 load pulse an internal by-pass allows to use the A2 value instead of the A1 value for

matches if A2 is either 0 or 1, thus allowing to generate matches even when A1 register is being loaded.

This approach allows a uniform channel operation for any A2 value, including 1 and 0.

In Figure 32-40 it is assumed that the channel and global prescalers are set to one, meaning that the channel

internal counter transition at every system clock cycle. FLAGs can be generated only on B1 matches when

MODE[1] is cleared, or on both A1 and B1 matches when MODE[1] is set. Since B1 FLAG occurs at the

cycle boundary, this flag can be used to indicate that A2 or B2 data written on cycle (n) were loaded to A1

or B1, respectively, thus generating matches in cycle (n+1).

match A1 negedge detection

A1 value

$000004

A1 match

A1 match negedge detection

output pin

EDPOL = 0

UCCNT

TIME

match B1 negedge detection

B1 match

B1 match negedge detection

B1 value

$000008

system clock

prescaler

A2 value

$000000

write to A2

$000000

A1 match posedge detection

match A1 posedge detection

no transition at this point

cycle n

cycle n+1

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