MAC7200 datasheet(797/976 Pages) FREESCALE

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Functional Description

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

719

Figure 32-40. OPWFMB A1 and B1 Registers Update and Flags

Figure 32-41 describes the operation of the Output Disable feature in OPWFMB mode. Differently from

the OPWFM mode, the output disable forces the channel output flip-flop to EDPOL bit value. This

functionality targets applications that use active high signals and a high to low transition at A1 match. In

this case EDPOL should be set to 0.

Figure 32-41. OPWFMB Mode with Active Output Disable

EDPOL = 0

cycle n

cycle n+1

cycle n+2

A1 value1

B1 value

B2 value

$000008

$000002

$000006

$000008

$000001

internal counter

$000004

$000006

MODE[0]= 1

A2 value1

$000002

$000004

$000006

$000002

$000004

$000006

$000008

$000006

Output pin

write to B2

write to A2

Match A1

Match B1

A1/B1 load signal

due to B1 match cycle n-1

FLAG set event

EDPOL = 0

cycle n

cycle n+1

cycle n+2

A1 value

B1 value

B2 value

$000008

$000002

$000006

$000008

$000001

internal counter

$000004

$000006

MODE[0]= 1

A2 value

$000002

$000004

$000006

$000002

$000004

$000006

$000008

$000006

Output pin

write to B2

write to A2

Match A1

Match B1

due to B1 match cycle n-1

FLAG set event

Output Disable

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