MAC7200 datasheet(799/976 Pages) FREESCALE

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Functional Description

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

721

NOTE

The internal counter may be running in the internal prescaler ratio, while the

selected time base may be running in a different prescaler ratio. The output

signal may produce an unexpected output if the dead time interval is greater

than the duty cycle of the PWM signal.

When operating with leading edge dead time insertion, the first match between A1 and the selected time

base clears the internal counter and switches the selected time base to the internal counter. When a match

occurs between register B1 and the selected time base, the output flip-flop is set to the value of the EDPOL

bit and the time base is switched to the selected counter bus. In the next match between register A1 and

the selected time base, the output flip-flop is set to the complement of the EDPOL bit. This sequence

repeats continuously.

When operating with trailing edge dead time insertion, the first match between A1 and the selected time

base sets the output flip-flop to the value of the EDPOL bit. In the next match between register A1 and the

selected time base, the internal counter is cleared and the selected time base is switched to the internal

counter. When a match occurs between register B1 and the selected time base, the output flip-flop is set to

the complement of the EDPOL bit and the time base is switched to the selected counter bus. This sequence

repeats continuously.

FLAG can be generated in the trailing edge of the output PWM signal when MODE[1] is cleared, or in

both edges, when MODE[1] is set.

At any time, the FORCMA or FORCMB bits are equivalent to a successful comparison on comparator A

or B with the exception that the FLAG bit is not set.

NOTE

When in freeze mode, the FORCMA or FORCMB bits only allow the

software to force the output flip-flop to the level corresponding of a match

on A or B respectively.

If subsequent matches occur on comparators A and B, the PWM pulses continue to be generated,

regardless of the state of the FLAG bit.

In order to achieve a duty cycle of 100%, both registers A1 and B1 must be set to the same value. When a

simultaneous match occurs between the selected time base and registers A1 and B1, the output flip-flop is

set at every period to the value of EDPOL bit and the selected time base switches to the selected counter

bus, allowing a new cycle to begin at any time, as previously described. 0% duty cycle is possible by

writing 0x000000 to register A. When a match occurs, the output flip-flop is set at every period to the

complement of EDPOL bit and the selected time base switches to the selected counter bus, allowing a new

cycle to begin at any time, as previously described. In both cases, FLAG is generated regardless of

MODE[1] bit.

NOTE

If A1 and B1 are set to the 0x000000, a 0% duty cycle waveform is

produced.

MAC7200 Datasheet(PDF) 799 Page - Freescale Semiconductor, Inc

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