MAC7200 datasheet(802/976 Pages) FREESCALE

802 / 976 page

Functional Description

MAC7200 Microcontroller Family Reference Manual, Rev. 2

724

Freescale Semiconductor

In this mode A1 matches always sets the internal counter to 0x000001. When operating with leading edge

dead time insertion the first A1 match sets the internal counter to 0x000001. When a match occurs between

following match between register A1 and the selected time base, the output flip-flop is set to the

complement of the EDPOL bit. This sequence repeats continuously. Figure 32-46 shows two cycles of a

Center Aligned PWM signal. Note that both A1 and B1 register values are changing within the same cycle

which allows to vary at the same time the duty cycle and dead time values.

Figure 32-46. Output PWMCB with Lead Dead Time Insertion

When operating with trailing edge dead time insertion, the first match between A1 and the selected time

base sets the output flip-flop to the value of the EDPOL bit and sets the internal counter to 0x000001. In

the second match between register A1 and the selected time base, the internal counter is set to 0x000001

and B1 matches are enabled. When the match between register B1 and the selected time base occurs the

output flip-flop is set to the complement of the EDPOL bit. This sequence repeats continuously.

EDPOL = 1

internal

time

base

internal counter is

set to 1 on A1 match

dead-time

A1 value

A2 value

B1 value

B2 value

write to B2

selected

counter bus

$000002

$000004

$000002

$000004

$000015

write to A2

$000013

$000001

$000002

$000004

$000015

$000013

$000020

dead-time

output flip-flop

FLAG set event

$000001

MAC7200 Datasheet(PDF) 802 Page - Freescale Semiconductor, Inc

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