MAC7200 datasheet(805/976 Pages) FREESCALE

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Functional Description

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

727

Figure 32-48. OPWMCB with 100% Duty Cycle (A1=4 and B1=3)

The output disable input, if enabled, cause the output flip-flop to transition to EDPOL inverted. This

feature allows to force the channel output pin to a safety state from the application stand point. The internal

channel matches continue to occur even in this case, thus generating Flags. As soon as the output disable

is deasserted the channel output pin is again controlled by A1 and B1 matches. Note that this process is

synchronous, meaning that the output channel pin transitions only on system clock edges.

It is important to notice that, like in OPWMB and OPWFMB modes, the match signal used to set or clear

the channel output flip-flop is generated on the deassertion of the channel combinational comparator

output signal which compares the selected time base with A1 or B1 register values. Please, refer to

Figure 32-38 which describes the delay from matches to output flip-flop transition in OPWFMB mode.

The operation of OPWMCB mode is similar to OPWFMB regarding matches and output pin transition.

32.13.1.1.17 Output Pulse Width Modulation (OPWM) Mode

Registers A1 and B1 define the leading and trailing edges of the PWM output pulse, respectively.

MODE[0] bit controls the transfer from register B2 to B1, which can be done either immediately

(MODE[0] cleared), providing the fastest change in the duty cycle, or at every match of register A1

(MODE[0] set).

The value loaded in register A1 is compared with the value on the selected time base. When a match on

comparator A occurs, the output flip-flop is set to the value of the EDPOL bit. When a match occurs on

comparator B, the output flip-flop is set to the complement of the EDPOL bit.

FLAG can be generated at match B, when MODE[1] is cleared, or in both matches, when MODE[1] is set.

At any time, the FORCMA and FORCMB bits allow the software to force the output flip-flop to the level

corresponding to a match on A or B respectively. Note that FLAG bit is not set by the FORCMA and

FORCMB operations.

$000001

dead time

$000020

dead time

write to A2

selected

counter bus

internal

time

base

$000004

A1 value

A2 value

B1 value

B2 value

$000004

$000001

output flip-flop

$000003

$000015

$000003

$000015

$000003

cycle n

cycle n+1

cycle n+2

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