MAC7200 datasheet(809/976 Pages) FREESCALE

Part #	MAC7200

Description	MAC7200 Microcontroller Family Reference Manual

PDF	976 Pages

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Manufacturer	FREESCALE [Freescale Semiconductor, Inc]

Direct Link	http://www.freescale.com

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809 / 976 page

Functional Description

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

731

Figure 32-52. OPWMB Mode with 0% Duty Cycle

Figure 32-53 describes the operation of the OPWMB mode with the Output Disable signal being asserted.

The output disable forces a transition in the output pin to the EDPOL bit value. After deasserted, the output

disable allows the output pin to transition at the following A1 or B1 match. Note that the output disable

does not modify the Flag bit behavior. Note that there is one system clock delay between the assertion of

the output disable signal and the transition of the output pin to EDPOL.

match A1 negedge detection

A1 value

$000004

A1 match

A1 match negedge detection

output pin

EDPOL = 0

Selected

TIME

match B1 negedge detection

B1 match

B1 match negedge detection

B1 value

$000008

clock

prescaler

A2 value

$000000

write to A2

$000000

A1 match posedge detection

match A1 posedge detection

cycle n

cycle n+1

FLAG bit set

counter bus

MAC7200 Datasheet(PDF) 809 Page - Freescale Semiconductor, Inc