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MAC7200 Datasheet(PDF) 811 Page - Freescale Semiconductor, Inc |
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MAC7200 Datasheet(HTML) 811 Page - Freescale Semiconductor, Inc |
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811 / 976 page ![]() Functional Description MAC7200 Microcontroller Family Reference Manual, Rev. 2 Freescale Semiconductor 733 Figure 32-55. lnput Programmable Filter submodule diagram The input signal is synchronized by system clock. When a state change occurs in this signal, the 5-bit counter starts counting up. As long as the new state is stable on the pin, the counter remains incrementing. If a counter overflows occurs, the new pin value is validated. In this case, it is transmitted as a pulse edge to the edge detector. If the opposite edge appears on the pin before validation (overflow), the counter is reset. At the next pin transition, the counter starts counting again. Any pulse that is shorter than a full range of the masked counter is regarded as a glitch and it is not passed on to the edge detector. A timing diagram of the input filter is shown in Figure 32-56. Figure 32-56. Input Programmable filter example 32.13.1.3 Clock Prescaler (CP) The CP divides the GCP output signal to generate a clock enable for the internal counter of the Unified Channels. It is a programmable 2-bit down counter. The GCP output signal is prescaled by the value defined in Table 32-7 according to the UCPRE[1:0] bits in UCCRn register. The output is clocked every time the counter reaches zero. Counting is enabled by setting the UCPREN bit in the UCCRn. The counter can be stopped at any time by clearing this bit, thereby stopping the internal counter in the Unified Channel. 32.13.1.4 Effect of Freeze on the Unified Channel When in debug mode, FRZ bit in the MCR register and the FREN bit in the UCCRn are both set, the internal counter and Unified Channel capture and compare functions are halted. The UC is frozen in its current state. IF3 filter out ipg_clk Prescaled Clock IF2 IF1 IF0 clk FCK EMIOSI 5-bit up counter clock Time selected clock EMIOSI 5-bit counter filter out IF [3:0]= 0010 |
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