Electronic Components Datasheet Search
  English  ▼

X  

Preview PDF HTML

MAC7200 Datasheet(PDF) 814 Page - Freescale Semiconductor, Inc

Part # MAC7200
Description  MAC7200 Microcontroller Family Reference Manual
PDF  976 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MAC7200 Datasheet(HTML) 814 Page - Freescale Semiconductor, Inc

Back Button MAC7200 Datasheet HTML 810Page - Freescale Semiconductor, Inc MAC7200 Datasheet HTML 811Page - Freescale Semiconductor, Inc MAC7200 Datasheet HTML 812Page - Freescale Semiconductor, Inc MAC7200 Datasheet HTML 813Page - Freescale Semiconductor, Inc MAC7200 Datasheet HTML 814Page - Freescale Semiconductor, Inc MAC7200 Datasheet HTML 815Page - Freescale Semiconductor, Inc MAC7200 Datasheet HTML 816Page - Freescale Semiconductor, Inc MAC7200 Datasheet HTML 817Page - Freescale Semiconductor, Inc MAC7200 Datasheet HTML 818Page - Freescale Semiconductor, Inc Next Button
Zoom Inzoom in Zoom Outzoom out
 814 / 976 page
background image
Initialization/Application Information
MAC7200 Microcontroller Family Reference Manual, Rev. 2
736
Freescale Semiconductor
Figure 32-58. Time base period when running with a pre scaler ratio greater than 1
32.14.2.2 Coherent Accesses
For IPWM, IPM and PEA modes, it is highly recommended that the software waits for a new FLAG set
event before start reading UCAn and UCBn registers to get a new measurement. The FLAG indicates that
new data has been captured and it is the only way to assure data coherency.
The FLAG set event can be detected by polling the FLAG bit or by enabling the interrupt or DMA request
generation.
Reading the UCAn register again in the same period of the last read of UCBn register may lead to
incoherent results. This will occur if the last read of UCBn register occurred after a disabled B2 to B1
transfer.
clock
pre scaled clock
internal counter
match value = 3
0
1
3
0
2
0
3
0
PRE SCALED CLOCK RATIO = 3
see note 1
Note 1: When a match occurs, the first clock cycle is used to clear the
internal counter, and only after a second edge of pre scaled clock
1
2
the counter will start counting.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com