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MAC7200 Datasheet(PDF) 813 Page - Freescale Semiconductor, Inc |
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MAC7200 Datasheet(HTML) 813 Page - Freescale Semiconductor, Inc |
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813 / 976 page ![]() Initialization/Application Information MAC7200 Microcontroller Family Reference Manual, Rev. 2 Freescale Semiconductor 735 32.14.2 Application Information Correlated output signals can be generated by all output operation modes. Bits OUDISn can be used to control the update of these output signals. In order to guarantee that the internal counters of correlated channels are incremented in the same clock cycle, the internal prescalers must be set up before enabling the global prescaler. If the internal prescalers are set after enabling the global prescaler, the internal counters may increment in the same ratio, but at a different clock cycle. It is recommended to drive Output Disable Input signals with the mts_flag_out signals of some UCs running in SAIC mode. When an output disable condition happens, the software interrupt routine must service the output channels before servicing the channels running SAIC. This procedure avoid glitches in the output pins. 32.14.2.1 Time Base Generation For MC, OPWFM and OPWM with internal clock source operation modes, the internal counter rate can be modified by configuring the clock pre scaler ratio. Figure 32-57 shows an example of a time base with pre scaler ratio equal to one. When the pre scaler is greater than one, the counter is immediately cleared on a match and then incremented in the next pre scaled clock edge, except when running in OPWFM mode or MC mode with internal clock source, in which case the counter will skip the next pre scaled clock edge and continue incrementing on subsequent edges, as shown in Figure 32-58. NOTE MCB, OPWFMB and OPWMB modes have a different behavior Figure 32-57. Time base period when running in the fastest pre scaler ratio clock pre scaled clock = 1 internal counter match value = 3 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 PRE SCALED CLOCK RATIO = 1 (bypassed) see note 1 Note 1: When a match occurs, the first clock cycle is used to clear the internal counter, starting another period. |
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