MAC7200 datasheet(812/976 Pages) FREESCALE

812 / 976 page

Initialization/Application Information

MAC7200 Microcontroller Family Reference Manual, Rev. 2

734

Freescale Semiconductor

During freeze, all registers are accessible. When the Unified Channel is operating in an output mode, the

force match functions remain available, allowing the software to force the output to the desired level.

Note that for input modes, any input events that may occur while the channel is frozen are ignored.

When exiting debug mode or freeze enable bit is cleared (FRZ in the MCR or FREN in the UCCRn

32.13.2 IP Bus Interface Unit (BIU)

The BIU provides the interface between the Internal interface bus (IIB) and the Peripheral Bus, allowing

communication among all submodules and this IP interface.

The BIU allows 8, 16 and 32 bits access. They are performed over a 32-bit data bus in a single cycle clock.

32.13.2.1 Effect of Freeze on the BIU

When the FRZ bit in the MCR register is set and the module is in debug mode, the operation of BIU is not

affected.

32.13.3 Global Clock Prescaler Submodule (GCP)

The GCP divides the system clock to generate a clock for the CPs of the Unified Channels. It is a

programmable 8-bit up counter. The main clock signal is prescaled by the value defined in Figure 32-7

according to the GPRE[7:0] bits in MCR register. The output is clocked every time the counter overflows.

Counting is enabled by setting the GPREN bit in the MCR. The counter can be stopped at any time by

clearing this bit, thereby stopping the internal counter in all the Unified Channels.

32.13.3.1 Effect of Freeze on the GCP

When the FRZ bit in the MCR register is set and the module is in debug mode, the operation of GCP

submodule is not affected, i.e., there is no freeze function in this submodule.

32.14 Initialization/Application Information

On resetting the eMIOS all of the Unified Channels enter GPIO input mode.

32.14.1 Considerations

Before changing an operating mode, the UC must be programmed to GPIO mode and UCAn and UCBn

registers must be updated with the correct values for the next operating mode. Then the UCCRn register

can be written with the new operating mode. If a UC is changed from one mode to another without

performing this procedure, the first operation cycle of the selected time base can be random, i.e., matches

can occur in random time if the contents of UCAn or UCBn were not updated with the correct value before

the time base matches the previous contents of UCAn or UCBn.

When interrupts are enabled, the software must clear the FLAG bits before exiting the interrupt service

routine.

MAC7200 Datasheet(PDF) 812 Page - Freescale Semiconductor, Inc