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MAC7200 Datasheet(PDF) 808 Page - Freescale Semiconductor, Inc |
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MAC7200 Datasheet(HTML) 808 Page - Freescale Semiconductor, Inc |
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808 / 976 page  Functional Description MAC7200 Microcontroller Family Reference Manual, Rev. 2 730 Freescale Semiconductor Figure 32-51. OPWMB Mode Matches and Flags Note that the output pin transitions are based on the negedges of the A1 and B1 match signals. Figure 32-51 shows in cycle(n+1) the value of A1 register being set to zero. In this case the match posedge is used instead of the negedge to transition the output flip-flop. Figure 32-52 describes the channel operation for 0% duty cycle. Note that the A1 match posedge signal occurs at the same time as the B1=8 negedge signal. In this case A1 match has precedence over B1 match, causing the output pin to remain at EDPOL bit value, thus generating a 0% duty cycle signal. 1 4 match A1 negedge detection 6 A1 value $000004 A1 match A1 match negedge detection output pin EDPOL = 0 TIME match B1 negedge detection B1 match B1 match negedge detection B1 value $000006 clock prescaler A2 value $000000 write to A2 $000000 A1 match posedge detection match A1 posedge detection 1 cycle n cycle n+1 8 6 FLAG bit set Selected counter bus |
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