MAC7200 datasheet(807/976 Pages) FREESCALE

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Functional Description

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

729

Figure 32-50. Output PWM with next period update

32.13.1.1.18 Pulse Width Modulation Buffered (OPWMB) Mode

OPWMB mode is used to generate pulses with programmable leading and trailing edge placement. An

external counter is selected from one of the counter buses. A1 register value defines the first edge and B1

the second edge. The output signal polarity is defined by the EDPOL bit. If EDPOL is zero, a negative

edge occurs when A1 matches the selected counter bus; and a positive edge occurs when B1 matches the

selected counter bus.

The A1 and B1 registers are double buffered and updated from A2 and B2, respectively, at the cycle

boundary. The load operation is similar to the OPWFMB mode. Please, refer to Figure 32-40 for more

information about A1 and B1 registers update.

FLAG can be generated at B1 matches, when MODE[1] is cleared, or in both, A1 and B1 matches, when

MODE[1] is set. If subsequent matches occur on comparators A and B, the PWM pulses continue to be

generated, regardless of the state of the FLAG bit.

FORCMA and FORCMB bits allow the software to force the output flip-flop to the level corresponding

to a match on A1 or B1 respectively. FLAG bit is not set by the FORCMA and FORCMB operations.

Following are described some rules applicable to the OPWMB mode:

•

B1 matches have precedence over A1 matches if they occur at the same time within the same

counter cycle

•

A1=0 match from cycle(n) has precedence over B1 match from cycle(n-1)

•

A1 matches are masked out if they occur after B1 match within the same cycle

•

Any value written to A2 or B2 on cycle(n) is loaded to A1 and B1 registers at the following cycle

boundary (assuming OUDISn is not asserted). Thus the new values will be used for A1 and B1

matches in cycle(n+1)

Figure 32-51 describes the operation of the OPWMB mode regarding A1 and B1 matches and the

transition of the channel output pin. In this example EDPOL is set to zero.

$FFFFFF

$001000

$000000

selected counter bus

Time

output flip-flop

A1 value1

write to B2

$000200

B1 value

B2 value2

$000200

$000900

Match B1

write to A1

$xxxxxx

$000200

$001000

$000900

and B2

$001000

Match A1

Match B1

Match A1

Notes: 1. UCAn = A1

2. UCBn =B2

$001000

$000900

A2 = A1 and A2 = A1 according to OUn bit

MODE[0]= 1

MAC7200 Datasheet(PDF) 807 Page - Freescale Semiconductor, Inc

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