MAC7200 datasheet(806/976 Pages) FREESCALE

806 / 976 page

Functional Description

MAC7200 Microcontroller Family Reference Manual, Rev. 2

728

Freescale Semiconductor

If subsequent matches occur on comparators A and B, the PWM pulses continue to be generated,

regardless of the state of the FLAG bit.

In order to achieve 100% duty cycle, both registers A1 and B1 must be set to the same value. When a

simultaneous match on comparators A and B occur, the output flip-flop is set at every period to the value

of EDPOL bit. 0% duty cycle is possible by writing 0x000000 to register A. When a match occurs, the

output flip-flop is set at every period to the complement of EDPOL bit. The transfer from register B2 to

B1 is still controlled by MODE[0] bit.

NOTE

If A1 and B1 are set to the 0x000000, a 0% duty cycle waveform is

produced.

Figure 32-49 and Figure 32-50 show the Unified Channel running in OPWM with immediate update and

next period update, respectivelly.

Figure 32-49. Output PWM with immediate update

$FFFFFF

$001000

$000000

selected counter bus

Time

Match A1

output flip-flop

A1 value1

update to A1

$000200

B1 value

B2 value2

$000900

Match B1

Match A1

update to A1

$xxxxxx

$000200

$001000

write to B2

Match B1

$000900

Notes: 1. UCAn = A1

2. UCBn = B2

$000900

$001000

A2 = A1according to OUn bit

B2 = B1according to OUn bit

MODE[0]= 0

MAC7200 Datasheet(PDF) 806 Page - Freescale Semiconductor, Inc

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