MAC7200 datasheet(801/976 Pages) FREESCALE

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Functional Description

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

723

32.13.1.1.16 Center Aligned Output PWM Buffered with Dead-Time (OPWMCB) Mode

This operation mode generates a center aligned PWM with dead time insertion to the leading or trailing

edge. A1 and B1 registers are double buffered to allow smooth output signal generation when changing

A2 or B2 registers values on the fly.

The selected counter bus must be running in up/down counter mode, as shown in Figure 32-33. The time

base selected for a channel configured to OPWMCB mode should be a channel configured to MCB mode.

BSL[1:0] bits select the time base. Register A1 contains the ideal duty cycle for the PWM signal and is

compared with the selected time base. Register B1 contains the dead time value and is compared against

the internal counter. For a leading edge dead time insertion, the output PWM duty cycle is equal to the

difference between register A1 and register B1, and for a trailing edge dead time insertion, the output

PWM duty cycle is equal to the sum of register A1 and register B1. Mode[0] bit selects between trailing

and leading dead time insertion, respectively.

NOTE

The internal prescaler of the OPWMCB channel should be set to the same

value of the MCB channel prescaler. These prescalers should also be

synchronized. In this case A1 and B1 registers represents the same timing

scale for duty cycle and dead time insertion.

Figure 32-45 describes the load of A1 and B1 registers which occurs when the selected counter bus reaches

the value one. This counter value defines the cycle boundary. Note that values written to A2 or B2 within

cycle (n) are loaded into A1 or B1 registers, respectively and used to generate matches in cycle (n+1).

Figure 32-45. OPWMCB A1 and B1 registers load

The OUDISn bit can be used to disable the A1 and B1 updates, thus allowing to synchronize the load on

these registers with the load of A1 or B1 registers in others channels. Note that using the update disable

bit A1 and B1 registers can be updated at the same counter cycle thus allowing to change both registers at

the same time.

A1 value

$000020

A2 value

$000020

$000015

$000016

$000015

A1/B1 load signal

Selected Counter == 1

Selected

TIME

write to A2

write to B2

write to A2

$000001

$000005

$000006

$000016

cycle n

cycle n+1

cycle n+2

Counter Bus]

B1 value

$000004

B2 value

$000004

$000005

$000006

$000005

$000006

MAC7200 Datasheet(PDF) 801 Page - Freescale Semiconductor, Inc

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