MAC7200 datasheet(798/976 Pages) FREESCALE

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Functional Description

MAC7200 Microcontroller Family Reference Manual, Rev. 2

720

Freescale Semiconductor

Note that the output disable has a synchronous operation, meaning that the assertion of the Output Disable

input pin causes the channel output flip-flop to transition to EDPOL at the next system clock cycle. If the

Output Disable input is deasserted the output pin transition at the following A1 or B1 match.

In Figure 32-41 it is assumed that the Output Disable input is enabled and selected for the Channel. Please,

refer to Section 32.12.2.8, “eMIOS Control Register (UCCRn)” for a detailed description about the ODIS

and ODISSL bits, respectively enable and selection of the Output Disable inputs.

The FORCMA and FORCMB bits allow the software to force the output flip-flop to the level

corresponding to a match on comparators A or B respectively. Similar to a B1 match FORCMB sets the

internal counter to 0x000001. The FLAG bit is not set by the FORCMA or FORCMB bits being asserted.

Figure 32-42 describes the generation of 100% and 0% duty cycle signals. It is assumed EDPOL =0 and

the resultant prescaler value is 1. Initially A1=0x000008 and B1=0x000008. In this case, B1 match has

precedence over A1 match, thus the output flip-flop is set to the complement of EDPOL bit. This cycle

corresponds to a 100% duty cycle signal. The same output signal can be generated for any A1 value greater

or equal to B1.

Figure 32-42. OPWFMB Mode from 100% to 0% Duty Cycle

A 0% duty cycle signal is generated if A1=0 as shown in Figure 32-42 cycle 9. In this case B1=0x000008

match from cycle 8 occurs at the same time as the A1=0x000000 match from cycle 9. Please, refer to

Figure 32-39 for a description of the A1 and B1 match generation. In this case A1 match has precedence

over B1 match and the output signal transitions to EDPOL.

32.13.1.1.15 Center Aligned Output Pulse Width Modulation with Dead-Time (OPWMC)

Mode

This operation mode generates a center aligned PWM with dead time insertion in the leading or trailing

edge. The selected counter bus must be running an up/down time base, as shown in Figure 32-31. BSL[1:0]

bits select the time base. Register A1 contains the ideal duty cycle for the PWM signal and is compared

with the selected time base. Register B1 contains the dead time value and is compared with the internal

counter. For a leading edge dead time insertion, the output PWM duty cycle is equal to the difference

between register A1 and register B1, and for a trailing edge dead time insertion, the output PWM duty

cycle is equal to the sum of register A1 and register B1. Mode[0] bit selects between trailing and leading

dead time insertion, respectively.

$000008

$000007

$000006

$000005

$000004

$000003

$000002

$000001

$000000

100%

UCCNT

EDPOL = 0

A1 value

B1 value

Output pin

$000008

Prescaler = 1

cycle 1

cycle 2

cycle 3

cycle 4

cycle 5

cycle 6

cycle 7

cycle 8

cycle 9

$000007

$000006

$000005

$000004

$000003

$000002

$000001

$000000

A2 value

MAC7200 Datasheet(PDF) 798 Page - Freescale Semiconductor, Inc

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