MAC7200 datasheet(795/976 Pages) FREESCALE

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Functional Description

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

717

When a match on comparator A occurs the output register is set to the value of EDPOL. When a match on

comparator B occurs the output register is set to the complement of EDPOL. B1 match also causes the

internal counter to transition to 1, thus re-starting the counter cycle.

Figure 32-38 describes the operation of the OPWFMB mode regarding output pin transitions and A1/B1

registers match events. Note that the output pin transition occurs when the A1 or B1 match signal is

deasserted which is indicated by the A1 match negedge detection signal. If register A1 is set to 0x000004

the output pin transitions 4 counter periods after the cycle had started, plus one system clock cycle. Note

that in the example shown in Figure 32-38 the internal counter prescaler is set to two.

Figure 32-38. OPWFMB A1 and B1 match to Output Register Delay

Figure 32-39 describes the generated output signal if A1 is set to 0. Since the counter does not reach zero

in this mode, the channel internal logic infers a match as if A1=1 with the difference that in this case, the

posedge of the match signal is used to trigger the output pin transition instead of the posedge used when

A1=1. Note that A1 posedge match signal from cycle (n+1) occurs at the same time as B1 negedge match

signal from cycle (n). This allows to use the A1 posedge match to mask the B1 negedge match when they

occur at the same time. The result is that no transition occurs on the output flip-flop and a 0% duty cycle

is generated.

match A1 negedge detection

A1 value

$000004

A1 match

A1 match negedge detection

output pin

EDPOL = 0

UCCNT

TIME

match B1 negedge detection

B1 match

B1 match negedge detection

B1 value

$000008

system clock

prescaler

MAC7200 Datasheet(PDF) 795 Page - Freescale Semiconductor, Inc