MAC7200 datasheet(792/976 Pages) FREESCALE

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Functional Description

MAC7200 Microcontroller Family Reference Manual, Rev. 2

714

Freescale Semiconductor

Figure 32-33. Modulus Counter Buffered (MCB) Up/Down Mode

Figure 32-34 describes in more detail the A1 register update process in up counter mode. The A1 load

signal is generated based on the detection of the internal counter reaching one and has the duration of one

system clock cycle. Note that during the load pulse A1 still holds its previous value. It is actually updated

only at the second system clock cycle.

Figure 32-34. MCB Mode A1 Register Update in Up Counter Mode

Figure 32-35 describes the A1 register update in up/down counter mode. Note that A2 can be written at

any time within cycle (n) in order to be used in cycle (n+1). Thus A1 receives this new value at the next

cycle boundary. Note that the update disable bits OUDISn can be used to disable the update of A1 register.

UCCNTn

TIME

write to A2

match A1

write to A2

$000001

$000005

$000006

$000007

FLAG set event

A1 value

$000006

$000005

$000007

$000005

$000007

A2 value

A1 value

$000008

$000001

internal counter

$000004

$000006

A2 value

$000008

$000004

$000006

$000002

$000004

$000006

write to A2

Match A1

A1 load signal

Match A1

Selected Counter = 1

Time

cycle n

cycle n+1

cycle n+2

MAC7200 Datasheet(PDF) 792 Page - Freescale Semiconductor, Inc

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