MAC7200 datasheet(793/976 Pages) FREESCALE

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Functional Description

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

715

Figure 32-35. MCB Mode A1 Register Update in Up/Down Counter Mode

32.13.1.1.13 Pulse Width and Frequency Modulation (OPWFM) Mode

In this mode, duty cycle of output signal is the value defined in register A1 plus one and the period is the

value defined in register B1 plus one. MODE[0] bit controls the transfer from register B2 to B1, which can

be done either immediately (MODE[0] cleared), providing the fastest change in the duty cycle, or at every

match of register A1 (MODE[0] set).

The internal counter is automatically selected as a time base, therefore the BSL[1:0] bits in register

UCCRn has no meaning. When a match on comparator A occurs, the output flip-flop is set to the value of

the EDPOL bit. When a match occurs on comparator B, the output flip-flop is set to the complement of the

EDPOL bit and the internal counter is cleared.

FLAG can be generated at match B, when MODE[1] is cleared, or in both matches, when MODE[1] is set.

At any time, the FORCMA and FORCMB bits allow the software to force the output flip-flop to the level

corresponding to a match on A or B respectively. Also, FORCMB clears the internal counter. Note that

the FLAG bit is not set by the FORCMA or FORCMB operations.

If subsequent comparisons occur on comparators A and B, the PWFM pulses continue to be output,

regardless of the state of the FLAG bit.

In order to achieve 100% duty cycle, both registers A1 and B1 must be set to the same value. When a

simultaneous match occurs on comparators A and B, the output flip-flop is set at every period to the value

of EDPOL bit. 0% duty cycle is possible by writing 0x000000 to register A. When a match occurs, the

output flip-flop is set at every period to the complement of EDPOL bit. The transfer from register B2 to

B1 is still controlled by MODE[0] bit.

NOTE

Writing 0x000000 to A1 and B1 produces a duty cycle of 0%.

Figure 32-36 shows the Unified Channel running in OPFWM mode with immediate register update and

Figure 32-37 shows the Unified Channel running in OPFWM mode with next period update PFWM mode.

A1 value

$000006

A2 value

$000006

$000005

$000006

$000005

A1 load signal

Selected Counter = 1

UCCNTn

TIME

write to A2

match A1

write to A2

$000001

$000005

$000006

cycle n

cycle n+1

cycle n+2

MAC7200 Datasheet(PDF) 793 Page - Freescale Semiconductor, Inc

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