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MAC7200 Datasheet(PDF) 893 Page - Freescale Semiconductor, Inc

Part # MAC7200
Description  MAC7200 Microcontroller Family Reference Manual
PDF  976 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MAC7200 Datasheet(HTML) 893 Page - Freescale Semiconductor, Inc

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Memory Map and Register Definition
MAC7200 Microcontroller Family Reference Manual, Rev. 2
Freescale Semiconductor
815
Base + 0x180
Port G: Pin 0 Configuration (CONFIG0)
16
R/W
A
Base + 0x182
Port G: Pin 1 Configuration (CONFIG1)
16
R/W
A
Base + 0x184
Port G: Pin 2 Configuration (CONFIG2)
16
R/W
A
Base + 0x186
Port G: Pin 3 Configuration (CONFIG3)
16
R/W
A
Base + 0x188
Port G: Pin 4 Configuration (CONFIG4)
16
R/W
A
Base + 0x18A
Port G: Pin 5 Configuration (CONFIG5)
16
R/W
A
Base + 0x18C
Port G: Pin 6 Configuration (CONFIG6)
16
R/W
A
Base + 0x18E
Port G: Pin 7 Configuration (CONFIG7)
16
R/W
A
Base + 0x190
Port G: Pin 8 Configuration (CONFIG8)
16
R/W
A
Base + 0x192
Port G: Pin 9 Configuration (CONFIG9)
16
R/W
A
Base + 0x194
Port G: Pin 10 Configuration (CONFIG10)
16
R/W
A
Base + 0x196
Port G: Pin 11 Configuration (CONFIG11)
16
R/W
A
Base + 0x198
Port G: Pin 12 Configuration (CONFIG12)
16
R/W
A
Base + 0x19A
Port G: Pin 13 Configuration (CONFIG13)
16
R/W
A
Base + 0x19C
Port G: Pin 14 Configuration (CONFIG14)
16
R/W
A
Base + 0x19E
Port G: Pin 15 Configuration (CONFIG15)
16
R/W
A
Base + 0x1A0
Port G: Port Wide Interrupt Flag (PORTIFR)
16
R/W
A
Base + 0x1A2
Reserved
Writing this register will have no effect.
Reading this register will return 0x00
Base + 0x1A4
Port G: Port Wide Data Read/Write (PORTDATA)
16
R/W
A
Base + 0x1A6
Port G: Port Wide Input (PORTIR)
16
R
A
Base + 0x1A8
Port G: Pin0 Data Read/Write (PINDATA0)
8
R/W
A
Base + 0x1A9
Port G: Pin1 Data Read/Write (PINDATA1)
8
R/W
A
Base + 0x1AA
Port G: Pin2 Data Read/Write (PINDATA2)
8
R/W
A
Base + 0x1AB
Port G: Pin3 Data Read/Write (PINDATA3)
8
R/W
A
Base + 0x1AC
Port G: Pin4 Data Read/Write (PINDATA4)
8
R/W
A
Base + 0x1AD
Port G: Pin5 Data Read/Write (PINDATA5)
8
R/W
A
Base + 0x1AE
Port G: Pin6 Data Read/Write (PINDATA6)
8
R/W
A
Base + 0x1AF
Port G: Pin7 Data Read/Write (PINDATA7)
8
R/W
A
Base + 0x1B0
Port G: Pin8 Data Read/Write (PINDATA8)
8
R/W
A
Base + 0x1B1
Port G: Pin9 Data Read/Write (PINDATA9)
8
R/W
A
Base + 0x1B2
Port G: Pin10 Data Read/Write (PINDATA10)
8
R/W
A
Base + 0x1B3
Port G: Pin11 Data Read/Write (PINDATA11)
8
R/W
A
Base + 0x1B4
Port G: Pin12 Data Read/Write (PINDATA12)
8
R/W
A
Base + 0x1B5
Port G: Pin13 Data Read/Write (PINDATA13)
8
R/W
A
Base + 0x1B6
Port G: Pin14 Data Read/Write (PINDATA14)
8
R/W
A
Base + 0x1B7
Port G: Pin15 Data Read/Write (PINDATA15)
8
R/W
A
Base + 0x1B8
to
Base + 0x1BF
Reserved
Writing this register will have no effect.
Reading this register will return 0x00
Table 34-11. Port Integration Module Memory Map (Continued)
Address
Use
Size
Access
Mode 1



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