MAC7200 datasheet(894/976 Pages) FREESCALE

894 / 976 page

Memory Map and Register Definition

MAC7200 Microcontroller Family Reference Manual, Rev. 2

816

Freescale Semiconductor

All registers are accessible via 8-bit, 16-bit or 32-bit accesses. However, 16-bit accesses must be aligned

to 16-bit boundaries, and 32-bit accesses must be aligned to 32-bit boundaries. As an example, the

CONFIG1 register for Port A is accessible by a 16-bit READ/WRITE to address ’Base + 0x000’, but

performing a 16-bit access to ’Base + 0x001’ is illegal.

34.6.1

This section consists of register descriptions in address order. Because 6 Ports (Port A, B, C, D, F, G) are

identical in their memory map, the following descriptions will only be given for a single Port.

34.6.1.1

Pin Configuration Register (Port A, B, C, D, F, G)

Each pin of Port A, B, C, D, F, G (16 per port) may be independently configured to select between

Peripheral and GPIO Modes, as well as the pin characteristics when GPIO Mode is selected. Note that

Base + 0x01C0

Base + 0x03BF

Reserved

See Note 2

Base + 0x03C0

Global Interrupt Status (GLBLINT)

Base + 0x03C2

PIM Configuration (PIMCONFIG)

R/W

Base + 0x03C4

TDI Pin Configuration (CONFIG_TDI)

R/W

Base + 0x03C6

TDO Pin Configuration (CONFIG_TDO)

R/W

Base + 0x03C8

TMS Pin Configuration (CONFIG_TMS)

R/W

Base + 0x03CA

TCK Pin Configuration (CONFIG_TCK)

R/W

Base + 0x03CC

Reserved

Writing this register will have no effect.

Reading this register will return 0x0000

Base + 0x03CE

RESET Pin Configuration (CONFIG_RESET)

R/W

Base + 0x03D0

Base + 0x03DF

Reserved

See Note 2

Base + 0x03E0

PORT32IR_AB

Base + 0x03E4

PORT32IR_CD

Base + 0x03E8

PORT32IR_F

Base + 0x03EC

PORT32IR_G

Base + 0x03F0

PORT32IR_BC

Base + 0x03F4

PORT32IR_D

Base + 0x03F8

PORT32IR_FG

Base + 0x03FC

Reserved

Writing this register will have no effect.

Reading this register will return 0x0000

Base + 0x0400

Base + 0x3FFF

Reserved

See Note 2

1. U = User Mode, S = Supervisor Mode, A = All (No restrictions)

2. If enabled at the SoC level, accessing these registers will cause bus aborts. Refer to the System Services Module

documentation for more details.

Table 34-11. Port Integration Module Memory Map (Continued)

Address

Use

Size

Access

Mode 1

MAC7200 Datasheet(PDF) 894 Page - Freescale Semiconductor, Inc

MAC7200 Datasheet(HTML) 894 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL