MAC7200 datasheet(896/976 Pages) FREESCALE

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Memory Map and Register Definition

MAC7200 Microcontroller Family Reference Manual, Rev. 2

818

Freescale Semiconductor

34.6.1.2

Pin Configuration Register (Port E)

NOTE

Because Port E implements only General Purpose Input (GPI) functionality,

the functionality of this register differs from the rest of the Ports. Careful

attention should be paid to the description of this register.

Each pin of Port E (16 pins) may be independently configured to select an optional pull-up or pull-down.

In order to use pins in Port E as ATD analog channels or external triggers, the pin must be configured to

Peripheral Mode.

3–2

PULL

Pull-up/Pull-down Enable Register. These bits serves a dual purpose by selecting the polarity of the active

interrupt edge as well as selecting a pull-up or pull-down device if enabled. Pull-ups/pull-downs may be

enabled or disabled when the pin is in either Peripheral or GPIO modes.

PIER

Pin Interrupt Enable Register. This bit masks the interrupt associated with a particular Pin Interrupt Flag

cleared, then no interrupt will occur if the Flag Register bit is set. Note that this bit does not affect the

setting/clearing of the Flag Register bit, it only determines whether a system interrupt will be generated or not.

0 Interrupt is masked

1 Interrupt is generated when PIFR is set by an active edge

PIFR

Pin Interrupt Flag Register. This bit signals that an active edge (i.e.-external interrupt) has been detected.

Writing a ’1’ to this bit clears the pending interrupt. Writing ’0’ has no effect. Interrupts are enabled on the pin

only when the pin is in GPIO Mode and is configured to be an input (MODE=0, DDR=0).

0 No active edge pending.

1 An active edge has been detected on the corresponding pin. If the PIER bit is also set, an interrupt will occur.

Table 34-13. CONFIGxx (Port A, B, C, D, F, G) Allowed Register Accesses

8-bit

16-bit

32-bit

READ

Allowed

Allowed 1

(Reads multiple CONFIG registers)

1. All 32-bit accesses must be aligned to 32-bit addresses (i.e.-0xxx0, 0xxx4, 0xxx8 or 0xxxC).

WRITE

Not Recommended 2

2. For backwards compatibility, 8-bit writes to the lower 8-bits (bit [7:0]) of a CONFIG register may be done if the upper 8-bits are

cleared (zero). For future compatibility, it is recommended to use a 16-bit read-mask-write operation on this register.

Allowed

Allowed 1

(Writes multiple CONFIG registers)

Table 34-12. CONFIGxx (Port A, B, C, D, F, G) Field Descriptions (Continued)

Field

Description

Value

Function

External Interrupt Edge

No Pull-up/Pull-down

Rising Edge

No Pull-up/Pull-down

Falling Edge

Pull-down Enabled

Rising Edge

Pull-up Enabled

Falling Edge

MAC7200 Datasheet(PDF) 896 Page - Freescale Semiconductor, Inc

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