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MAC7200 Datasheet(PDF) 897 Page - Freescale Semiconductor, Inc |
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MAC7200 Datasheet(HTML) 897 Page - Freescale Semiconductor, Inc |
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897 / 976 page ![]() Memory Map and Register Definition MAC7200 Microcontroller Family Reference Manual, Rev. 2 Freescale Semiconductor 819 Offset see Table 34-11 Access: see Table 34-15 15 14 13 12 11 10 987 6543210 R 0000 0000 00 0 PULL PIER PIFR W Reset 0000 0000000 00000 Figure 34-4. Pin Configuration Register (CONFIGxx, Port E) Table 34-14. CONFIGxx (Port E) Field Descriptions Field Description 15–8 Reserved, should be cleared. 7 MODE Pin Mode Register. This bit switches the associated pin between Peripheral and GPI Modes 0GPI Mode 1 Peripheral Mode 6–4 Reserved, should be cleared. 3–2 PULL Pull-up/Pull-down Enable Register. These bits serves a dual purpose by selecting the polarity of the active interrupt edge as well as selecting a pull-up or pull-down device if enabled. Pull-ups/pull-downs may be enabled or disabled anytime, but only take effect when the pin is in GPIO mode. In Peripheral mode the peripheral takes control of the pull configuration and interrupt functionality is disabled. 1 PIER Pin Interrupt Enable Register. This bit masks the interrupt associated with a particular Pin Interrupt Flag Register bit. If this bit is set, an interrupt will occur if the corresponding Flag Register bit is set. If this bit is cleared, then no interrupt will occur if the Flag Register bit is set. Note that this bit does not affect the setting/clearing of the Flag Register bit, it only determines whether a system interrupt will be generated or not. 0 Interrupt is masked 1 Interrupt is generated when PIFR is set by an active edge 0 PIFR Pin Interrupt Flag Register. This bit signals that an active edge (i.e.-external interrupt) has been detected. Writing a ’1’ to this bit clears the pending interrupt. Writing ’0’ has no effect. Interrupts are enabled on the pin only when the pin is in GPI Mode (MODE=0). 0 No active edge pending. 1 An active edge has been detected on the corresponding pin. If the PIER bit is also set, an interrupt will occur. Table 34-15. CONFIGxx (Port E) Allowed Register Accesses 8-bit 16-bit 32-bit READ Not Recommended 1 Allowed Allowed 2 (Reads multiple CONFIG registers) WRITE Not Recommended 1 Allowed Allowed 2 (Writes multiple CONFIG registers) Value Function External Interrupt Edge 00 No Pull-up/Pull-down Rising Edge 01 No Pull-up/Pull-down Falling Edge 10 Pull-down Enabled Rising Edge 11 Pull-up Enabled Falling Edge |
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