MAC7200 datasheet(895/976 Pages) FREESCALE

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Memory Map and Register Definition

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

817

some pins do not have Peripheral Mode functionality. In this case, when the pin is programmed to be in

Peripheral Mode, it will configured to be an output and will drive a low (0) signal out.

Offset see Table 34-11

Access: see Table 34-13

987

6543210

000

MODE

DDR

PULL

PIER

PIFR

Reset

0000

0000000

00000

Figure 34-3. Pin Configuration Register (CONFIGxx, Port A, B, C, D, F, G)

Table 34-12. CONFIGxx (Port A, B, C, D, F, G) Field Descriptions

Field

Description

SLEWDIS

Slew Rate Disable Register. This bit enables/disables slew rate control. If enabled, the Slew Rate Control

and the Slew Rate Control Register has no effect.

0 Slew rate control enabled

1 Slew rate control disabled

14–9

Reserved, should be cleared.

8–7

MODE

Pin Mode Register. These bits switch the associated pin between Peripheral and GPI Modes.

00 GPIO Mode

01 Primary Peripheral Mode

10 Secondary Peripheral Mode

11 Tertiary Peripheral Mode

Note: It is not possible to use pad PD2 as a General Purpose Output. Pad PD2 behaves virtually identically if

it is configured in General Purpose Output Mode or in Peripheral Mode except that, in Peripheral Mode,

the open drain functionality is disabled. In GPO Mode, the open drain functionality may be

enabled/disabled via the ODER bit.

Note: If a Secondary Peripheral is not defined for the pin, then setting the Pin Mode to Secondary Peripheral

Mode is exactly equivalent to setting it to Primary Peripheral Mode. The same is true for Tertiary

Peripheral Mode.

Note: Currently, only pins PA8 and PA9 allow usage of non-primary peripheral mode. For all other pins only

MODE[1:0] values of 2’b00 or 2’b01 are allowed.

DDR

Data Direction Register. This bit switches the pin between output and input when the pin is in GPIO Mode

(MODE=0).

0 Pin is an input

1 Pin is an output

ODER

Open Drain Enable Register. This bit configures the pin to be open drain when the pin is in GPIO Mode

(MODE=0).

0 Open Drain is disabled on the pin

1 Open Drain is enabled on the pin

SLEW

Slew Rate Control Register. This bit selects the slew rate of the pin, and is used only when the pin is selected

as an output and the Slew Rate Enable is set.

0 Fast slew rate selected

1 Slow slew rate selected

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