MAC7200 datasheet(898/976 Pages) FREESCALE

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Memory Map and Register Definition

MAC7200 Microcontroller Family Reference Manual, Rev. 2

820

Freescale Semiconductor

34.6.1.3

Port Wide Interrupt Flag Register

34.6.1.4

Port Wide Data Register (Port A, B, C, D, F, G)

1. For future compatibility, it is recommended to use a 16-bit or 32-bit read-mask-write operations on this register.

2. All 32-bit accesses must be aligned to 32-bit addresses (i.e.-0xxx0, 0xxx4, 0xxx8 or 0xxxC).

Offset see Table 34-11

Access: see Table 34-17

987

6543210

R IFR15 IFR14 IFR13 IFR12 IFR11 IFR10 IFR9

IFR8

IFR7

IFR6

IFR5

IFR4

IFR3

IFR2

IFR1

IFR0

Reset

0000

0000000

00000

Figure 34-5. Port Wide Interrupt Flag Register (PORTIFR)

Table 34-16. PORTIFR Field Descriptions

Field

Descriptions

15–0

IFRxx

Interrupt Flag bit. This 16-bit register allows the reading and clearing of the PIFR (Pin Interrupt Flag Register)

bits for all pins in a single bus access. This is useful for determining the exact source of an interrupt/wakeup,

and for clearing multiple interrupts simultaneously. Writing a ’1’ to a bit clears the corresponding pending

interrupt. Writing ’0’ has no effect. Interrupts are enabled on the pin only when the pin is in GPIO Mode and is

configured to be an input (MODE=0, DDR=0). Note that writing/reading to/from a bit in this register is

functionally identical to writing/reading to/from the PIFR bit in the CONFIG register for that pin. As an example,

setting IFR1 is the same as setting the PIFR bit in register CONFIG1.

Table 34-17. PORTIFR Allowed Register Accesses

8-bit

16-bit

32-bit

READ

Allowed

Not Recommended

WRITE

Allowed

Not Recommended

Offset see Table 34-11

Access: see Table 34-19

987

6543210

DATA

Reset

0000

0000000

00000

Figure 34-6. Port Wide Data Register (PORTDATA, Port A, B, C, D, F, G)

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