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MAC7200 Datasheet(PDF) 900 Page - Freescale Semiconductor, Inc |
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MAC7200 Datasheet(HTML) 900 Page - Freescale Semiconductor, Inc |
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900 / 976 page ![]() Memory Map and Register Definition MAC7200 Microcontroller Family Reference Manual, Rev. 2 822 Freescale Semiconductor 34.6.1.6 Port Wide Input Register (Port A, B, C, D, F, G) 34.6.1.7 Port Wide Input Register (Port E) NOTE Because Port E implements only General Purpose Input (GPI) functionality, the functionality of this register differs from the rest of the Ports. Careful attention should be paid to the description of this register. Table 34-21. PORTDATA (Port E) Allowed Register Accesses 8-bit 16-bit 32-bit READ Allowed Allowed Not Recommended WRITE Not Allowed Not Allowed Not Allowed Offset see Table 34-11 Access: see Table 34-23 15 14 13 12 11 10 987 6543210 RDATA W Reset 0/11 0/11 0/11 0/11 0/11 0/11 0/11 0/11 0/11 0/11 0/11 0/11 0/11 0/11 0/11 0/11 1 The reset value of this register depends on the value of the pins at the time of the first register READ after reset. Figure 34-8. Port Wide Input Register (PORTIR, Port A, B, C, D, F, G) Table 34-22. PORTIR (Port A, B, C, D, F, G) Field Descriptions Field Description 15–0 DATA 16-bit Port Read Register. This 16-bit read-only register reads back the value on the associated pins, and can be used to detect overload or short circuit conditions on output pins. Functionally, it is related to the PORTDATA register in the following manner: • When the pin is configured as an input (DDR=0), reading the PORTDATA and PORTIR registers will yield the same result • When the pin is configured as an output (DDR=1), reading the PORTIR register will yield the value on the pin, while reading the PORTDATA register will yield the value in the PORTDATA register. If the pin is in Peripheral Mode (MODE=1), then the value in the PORTDATA register may not be the same as the value driven onto the pin by the peripheral. Note: There is a 2 cycle synchronization that is performed on pin values before registering the value. Therefore, there must be a minimum 2 system clock cycles between the time a pin is driven, and the time that the register read is performed. Note: Not all Ports are available on all packages. In the case where a port, or some pins in a port are not available on a package, the value of the corresponding bit(s) in the PORTIR register are indeterminate. Table 34-23. PORTIR (Port A, B, C, D, F, G) Allowed Register Accesses 8-bit 16-bit 32-bit READ Allowed Allowed Not Allowed WRITE Not Allowed Not Allowed Not Allowed |
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