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MAC7200 Datasheet(PDF) 948 Page - Freescale Semiconductor, Inc |
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MAC7200 Datasheet(HTML) 948 Page - Freescale Semiconductor, Inc |
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948 / 976 page ![]() Oscillator Characteristics MAC7200 Microcontroller Family Reference Manual, Rev. 2 870 Freescale Semiconductor XCLKS signal at the rising edge of the RESET signal. Before asserting the oscillator to the internal system clock distribution subsystem, the quality of the oscillator output clock is checked for each start from either power on reset (POR) or reset after a Clock Monitor Failure. tCQOUT specifies the maximum time before switching to the internal self clock mode after POR if a proper oscillator clock output is not detected. The quality check also determines the minimum oscillator start-up time tUPOSC. The device also features a Crystal Monitor. A Crystal Monitor Failure is asserted if the frequency of the incoming clock signal is below the Crystal Monitor Assert Frequency fCMFA. NOTE The use of overtone resonators (Ceramic or Crystal) is not recommended. NOTE The oscillators on the MAC71xx and MAC72xx are different designs. You should characterize your oscillator design if you switch between the two devices. Table A-14. Oscillator Characteristics Num C Rating Symbol Min Typ Max Unit H1a C Crystal oscillator frequency (ALC Mode)1 1. XCLKS negated (1) during reset fOSC 2 2. If CLKSEL[PLLSEL] is clear then the system clock (fSYS) is equal to fOSC, otherwise it is equal to fVCO. Throughout this document, tSYS is used to specify a unit of time equal to 1 / fSYS. 4.0 — 20 (MAC72x2) 40 (MAC72x1) MHz H1b C External Clock Frequency (Oscillator bypassed)3 3. XCLKS asserted (0) during reset fOSC 0.5 — 70 MHz H2 C Crystal oscillator reference duty cycle tDUTY 40 — 60 % H3 C Startup Current IOSC 1.2 — — mA H4 D Supply Voltage VDDPLL 3.0 3.3 3.6 V H5 D Supply Current IOSC —— 3 mA H6 C Oscillator start-up time (ALC Mode) tUPOSC —5(4) 4. fosc = 8 MHz, CLOAD = 16.5 pF, CEXTAL = 33 pF, CXTAL = 33pF. 10(5) 5. Maximum value is for extreme cases using high Q, low frequency crystals ms H7 D Clock Quality check time-out tCQOUT 0.45 — 2.5 s H8 D Clock Monitor Failure Assert Frequency fCMFA 100 200 400 KHz H9 D External Clock Duty Cycle — 40/60 — H10 D External Clock rise time tEXTR —— 1 ns H11 D External Clock fall time tEXTF —— 1 ns |
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