AM3892 datasheet(44/299 Pages) TI

44 / 299 page

AM3894

AM3892

SPRS681A – OCTOBER 2010 – REVISED MARCH 2011

www.ti.com

3.2

Terminal Functions

The terminal functions tables identify the external signal names, the associated pin (ball) numbers along

with the mechanical package designator, the pin type, whether the pin has any internal pullup or pulldown

resistors, and a functional pin description. Bolded pin names denote the muxed pin function being

described in each table. For more detailed information on device configurations, peripheral selection,

multiplexed/shared pin, and see Section 4, Device Configurations.

3.2.1

Boot Configuration

Table 3-1. Boot Terminal Functions

SIGNAL

TYPE(1)

OTHER(2) (3)

MUXED

DESCRIPTION

NAME

NO.

BOOT

Boot Mode inputs. Select the peripheral over which the Host ARM Cortex™-A8 will boot.

GPMC_A[5]/GP0[13]/

GPMC, GP0

AE2

BTMODE[4]

PINCTRL226

GPMC_A[4]/GP0[12]/

GPMC, GP0

AE1

BTMODE[3]

PINCTRL225

PULL: IPU / DIS

GPMC_A[3]/GP0[11]/

GPMC, GP0

Boot Mode Selection pins. For boot mode information,

AE3

DRIVE: Z / Z

BTMODE[2]

PINCTRL224

see Table 4-5.

DVDD_3P3

GPMC_A[2]/GP0[10]/

GPMC, GP0

AE4

BTMODE[1]

PINCTRL223

GPMC_A[1]/GP0[9]/

GPMC, GP0

AE5

BTMODE[0]

PINCTRL222

DEVICE CONTROL

GPMC CS0 default Data Bus Width input

PULL: IPU / DIS

GPMC_A[8]/GP0[16]/

GPMC, GP0

AD4

DRIVE: Z / Z

0 = 8-bit data bus

CS0BW

PINCTRL229

DVDD_3P3

1 = 16-bit data bus

GPMC_A[7]/GP0[15]/

GPMC, GP0

GPMC CS0 default Address/Data multiplexing mode

AD3

CS0MUX[1]

PINCTRL228

input

PULL: IPU / DIS

00 = Not multiplexed

DRIVE: Z / Z

GPMC_A[6]/GP0[14]/

GPMC, GP0

01 = A/A/D muxed

DVDD_3P3

AD8

CS0MUX[0]

PINCTRL227

10 = A/D muxed

11 = Reserved

GPMC CS0 default GPMC_Wait enable input

PULL: IPD / DIS

GPMC_A[9]/GP0[17]/

GPMC, GP0

AD2

DRIVE: Z / Z

0 = Wait disabled

CS0WAIT

PINCTRL230

DVDD_3P3

1 = Wait enabled

(1)

I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal.

(2)

PULL: A / B, where:

A is the state of the internal pull resistor during POR reset

B is the state of the internal pull resistor after POR and Warm reset are de-asserted and during Warm reset

IPD = Internal Pulldown Enabled, IPU = Internal Pullup Enabled, DIS = Internal Pull Disabled

DRIVE: A / B, where;

A is the driving state of the pin during POR reset

B is the driving state of the pin after POR and Warm reset are de-asserted and during Warm reset

H = Driving High, L = Driving Low, Z = 3-State

For more detailed information on pullup/pulldown resistors and situations where external pullup/pulldown resistors are required, see

Section 4.2.1, Pullup/Pulldown Resistors.

(3)

Specifies the operating I/O supply voltage for each signal.

Device Pins

Submit Documentation Feedback

Product Folder Link(s): AM3894 AM3892

AM3892 Datasheet(PDF) 44 Page - Texas Instruments

AM3892 Datasheet(HTML) 44 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL