AM3892 datasheet(6/299 Pages) TI

6 / 299 page

AM3894

AM3892

SPRS681A – OCTOBER 2010 – REVISED MARCH 2011

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Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

This revision history highlights the technical changes made to the document in this revision.

AM389x Revisions

SEE

ADDITIONS/MODIFICATIONS/DELETIONS

Section 1.1

Features:

Modified GPMC Chip Selects feature item

Section 1.2

Description:

Modified last paragraph

Section 2.5

Added new section: Inter-Processor Communication

Moved Section 2.5.1, Mailbox Module, and Section 2.5.2, Spinlock Module, under Inter-Processor

Communication

Section 2.5.1.1

Added new section: Mailbox Registers

Section 2.5.2

Spinlock Module:

Modified number of spinlocks in last paragraph

Section 2.5.2.1

Added new section: Spinlock Registers

Section 2.8.1

L3 Memory Map:

Change Block for Address 0x47C0 0000 - 0x47FF FFFF to Reserved in Table 2-19, L3 Memory Map

Deleted L4 Firewall Peripheral section

Section 2.8.4

Cortex™-A8 Memory Map:

Changed Region for Address 0x47C0 0000 - 0x47FF FFFF to Reserved in Table 2-23, Cortex™-A8 Memory

Map

Section 3.2.1

Boot Configuration:

Modified GPMC_A[7]/GP0[15]/CS0MUX[1] and GPMC_A[6]/GP0[14]/CS0MUX[0] Signal Description in

Table 3-1

Section 3.2.11

Peripheral Component Interconnect Express (PCIe) Signals:

Modified PCIE_TXP|N0/1 and PCIE_RXP|N0/1 Signal Descriptions in Table 3-14, PCIe Terminal Functions

Section 3.2.23

Supply Voltages:

Modified DVDD1P8 Signal Description in Table 3-30, Supply Terminal Functions

Section 4.1

Control Module:

Modified Acronym and Register Name for Hex Address 0x4814 0608 and 0x4814 060C in Table 4-4, Device

Configuration Registers Summary

Section 4.4

Pin Multiplexing Control:

Modified first paragraph

Section 4.5

Moved How to Handle Unused Pins up to this section

Section 5

System Interconnect:

Modified second paragraph

Section 5.1

L3 Interconnect:

Modified Figure 5-1, Interconnect Overview

Modified Table 5-1, L3 Master/Slave Connectivity

Section 5.2

L4 Interconnect:

Modified second paragraph

Modified Figure 5-2, L4 Architecture

Modified Table 5-2, L4 Peripheral Connectivity

Section 6

Device Operating Conditions:

Added MIN and MAX columns, modified ESD parameters, added Footnote (6), modified Footnotes (7) and

(8) in Section 6.1, Absolute Maximum Ratings Over Operating Case Temperature Range

Section 7.1.4

SmartReflex:

Modified first paragraph

Contents

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