AM3892 datasheet(71/299 Pages) TI

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AM3894

AM3892

www.ti.com

SPRS681A – OCTOBER 2010 – REVISED MARCH 2011

3.2.11 Peripheral Component Interconnect Express (PCIe) Signals

Table 3-14. PCIe Terminal Functions

SIGNAL

TYPE(1)

OTHER(2)

DESCRIPTION

NAME

NO.

PCIE_TXP0

AB31

PCIE Transmit Data Lane 0.

VDDR_PCIE

When the PCIe SERDES are powered down, or if this lane is not used,

PCIE_TXN0

AB30

these pins should be left unconnected.

PCIE_RXP0

Y29

PCIE Receive Data Lane 0.

VDDR_PCIE

When the PCIe SERDES are powered down, or if this lane is not used,

PCIE_RXN0

V29

these pins should be left unconnected.

PCIE_TXP1

Y27

PCIE Transmit Data Lane 1.

VDDR_PCIE

When the PCIe SERDES are powered down, or if this lane is not used,

PCIE_TXN1

AB28

these pins should be left unconnected.

PCIE_RXP1

V31

PCIE Receive Data Lane 1.

VDDR_PCIE

When the PCIe SERDES are powered down, or if this lane is not used,

PCIE_RXN1

V30

these pins should be left unconnected.

SERDES_CLKP

AB34

VDD_LJCB

PCIE Serdes Reference Clock Inputs. Shared between PCI Express and

Serial ATA. When neither PCI Express nor Serial ATA are used, these

SERDES_CLKN

AB33

VDD_LJCB

pins should be left unconnected.

(1)

I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal.

(2)

Specifies the operating I/O supply voltage for each signal.

Device Pins

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