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AM3892 Datasheet(PDF) 16 Page - Texas Instruments |
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AM3892 Datasheet(HTML) 16 Page - Texas Instruments |
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16 / 299 page  AM3894 AM3892 SPRS681A – OCTOBER 2010 – REVISED MARCH 2011 www.ti.com Table 2-13. CM_SGX Register Summary HEX ADDRESS ACRONYM REGISTER NAME 0x4818 0900 CM_SGX_CLKSTCTRL SGX530 clock domain power state transition 0x4818 0920 CM_SGX_SGX_CLKCTRL SGX530 clock management control Table 2-14. PRM_ACTIVE Register Summary HEX ADDRESS ACRONYM REGISTER NAME 0x4818 0A00 PM_ACTIVE_PWRSTCTRL Active power state control 0x4818 0A04 PM_ACTIVE_PWRSTST Active power domain state status 0x4818 0A10 RM_ACTIVE_RSTCTRL Active domain reset control release 0x4818 0A14 RM_ACTIVE_RSTST Active domain reset source log Table 2-15. PRM_DEFAULT Register Summary HEX ADDRESS ACRONYM REGISTER NAME 0x4818 0B00 PM_DEFAULT_PWRSTCTRL Default power state 0x4818 0B04 PM_DEFAULT_PWRSTST Default power domain state 0 status 0x4818 0B10 RM_DEFAULT_RSTCTRL Default subsystem reset control release 0x4818 0B14 RM_DEFAULT_RSTST Default domain reset source log Table 2-16. PRM_SGX Register Summary HEX ADDRESS ACRONYM REGISTER NAME 0x4818 0F00 PM_SGX_PWRSTCTRL SGX530 power state control 0x4818 0F04 RM_SGX_RSTCTRL SGX530 domain reset control release 0x4818 0F10 PM_SGX_PWRSTST SGX530 power domain state status 0x4818 0F14 RM_SGX_RSTST SGX530 domain reset source log Table 2-17. CM_ALWON Register Summary HEX ADDRESS ACRONYM REGISTER NAME 0x4818 1400 CM_ALWON_L3_SLOW_CLKSTCTRL L3 clock domain power state transition 0x4818 1404 CM_ETHERNET_CLKSTCTRL EMAC clock domain power state transition 0x4818 1408 CM_ALWON_L3_MED_CLKSTCTRL L3 clock domain power state transition 0x4818 1414 CM_ALWON_OCMC_0_CLKSTCTRL OCMC 0 clock domain power state transition 0x4818 1418 CM_ALWON_OCMC_1_CLKSTCTRL OCMC 1 clock domain power state transition 0x4818 141C CM_ALWON_MPU_CLKSTCTRL MPU clock domain power state transition 0x4818 1420 CM_ALWON_SYSCLK4_CLKSTCTRL SYSCLK4 clock domain power state transition 0x4818 1424 CM_ALWON_SYSCLK5_CLKSTCTRL SYSCLK5 clock domain power state transition 0x4818 1428 CM_ALWON_SYSCLK6_CLKSTCTRL SYSCLK6 clock domain power state transition 0x4818 142C CM_ALWON_RTC_CLKSTCTRL RTC clock domain power state transition 0x4818 1430 CM_ALWON_L3_FAST_CLKSTCTRL L3 clock domain power state transition 0x4818 1540 CM_ALWON_MCASP0_CLKCTRL McASP 0 clock management control 0x4818 1544 CM_ALWON_MCASP1_CLKCTRL McASP 1 clock management control 0x4818 1548 CM_ALWON_MCASP2_CLKCTRL McASP 2 clock management control 0x4818 154C CM_ALWON_MCBSP_CLKCTRL McBSP clock management control 0x4818 1550 CM_ALWON_UART_0_CLKCTRL UART 0 clock management control 0x4818 1554 CM_ALWON_UART_1_CLKCTRL UART 1 clock management control 0x4818 1558 CM_ALWON_UART_2_CLKCTRL UART 2 clock management control 0x4818 155C CM_ALWON_GPIO_0_CLKCTRL GPIO 0 clock management control 0x4818 1560 CM_ALWON_GPIO_1_CLKCTRL GPIO 1 clock management control 16 Device Overview Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM3894 AM3892 |
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