AM3892 datasheet(10/299 Pages) TI

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ARM Cortex™-A8

NEON

ETM

256KB L2$

32KB L1I$ 32KB L1D$

Arbiter

128

ICECrusher

48KB ROM

64KB RAM

ARM Cortex-A8

Interrupt Controller

(AINTC)

DMM

128

SYSCLK2

128

System Events

DEVOSC

Trace

Debug

AM3894

AM3892

SPRS681A – OCTOBER 2010 – REVISED MARCH 2011

www.ti.com

Table 2-2. Characteristics of the Processor (continued)

HARDWARE FEATURES

AM3894/AM3892

Cycle Time

0.67 ns

Core Logic (V)

1.0 V with Required AVS Capability

USB Logic (V)

0.9 V

Voltage

RAM (V)

1.0 V

I/O (V)

1.5 V, 1.8 V, 3.3 V

Package

25 x 25 mm

1031-Pin BGA (CYG)

Process Technology

µm

0.04 µm

Product Preview (PP),

Product Status(1)

Advance Information (AI),

or Production Data (PD)

(1)

PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other

specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.

2.3

ARM Subsystem

The ARM subsystem is designed to give the ARM Cortex-A8 master control of the device. In general, the

ARM Cortex-A8 is responsible for configuration and control of the various subsystem, peripherals, and

external memories.

The ARM subsystem includes the following features:

•

ARM Cortex-A8 RISC processor:

–

ARMv7 ISA plus Thumb®-2, Jazelle-X, and media extensions

–

NEON floating-point unit

–

Enhanced memory management unit (MMU)

–

Little Endian

–

32KB L1 instruction cache

–

32KB L1 data cache

–

256KB L2 cache

•

Foresight embedded trace module (ETM)

•

ARM Cortex-A8 interrupt controller (AINTC)

•

64KB internal RAM

•

48KB internal public ROM.

Figure 2-1. ARM Cortex-A8 Subsystem Block Diagram

Device Overview

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