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AM3892 Datasheet(PDF) 15 Page - Texas Instruments |
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AM3892 Datasheet(HTML) 15 Page - Texas Instruments |
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15 / 299 page  AM3894 AM3892 www.ti.com SPRS681A – OCTOBER 2010 – REVISED MARCH 2011 Table 2-10. CM_DPLL Register Summary (continued) HEX ADDRESS ACRONYM REGISTER NAME 0x4818 0334 CM_SYSCLK13_CLKSEL SYSCLK13 clock divider value select 0x4818 0338 CM_SYSCLK15_CLKSEL SYSCLK15 clock divider value select 0x4818 0340 CM_VPB3_CLKSEL Video PLL B3 clock divider value select 0x4818 0344 CM_VPC1_CLKSEL Video PLL C1 clock divider value select 0x4818 0348 CM_VPD1_CLKSEL Video PLL D1 clock divider value select 0x4818 034C CM_SYSCLK19_CLKSEL SYSCLK19 clock divider value select 0x4818 0350 CM_SYSCLK20_CLKSEL SYSCLK20 clock divider value select 0x4818 0354 CM_SYSCLK21_CLKSEL SYSCLK21 clock divider value select 0x4818 0358 CM_SYSCLK22_CLKSEL SYSCLK22 clock divider value select 0x4818 035C CM_APA_CLKSEL Audio PLL A clock divider value select 0x4818 0370 CM_SYSCLK14_CLKSEL SYSCLK14 clock mux select line 0x4818 0374 CM_SYSCLK16_CLKSEL SYSCLK16 clock mux select line 0x4818 0378 CM_SYSCLK18_CLKSEL SYSCLK18 clock mux select line 0x4818 037C CM_AUDIOCLK_MCASP0_CLKSEL McASP0 audio clock mux select line 0x4818 0380 CM_AUDIOCLK_MCASP1_CLKSEL McASP1 audio clock mux select line 0x4818 0384 CM_AUDIOCLK_MCASP2_CLKSEL McASP2 audio clock mux select line 0x4818 0388 CM_AUDIOCLK_MCBSP_CLKSEL McBSP audio clock mux select line 0x4818 0390 CM_TIMER1_CLKSEL Timer1 clock mux select line 0x4818 0394 CM_TIMER2_CLKSEL Timer2 clock mux select line 0x4818 0398 CM_TIMER3_CLKSEL Timer3 clock mux select line 0x4818 039C CM_TIMER4_CLKSEL Timer4 clock mux select line 0x4818 03A0 CM_TIMER5_CLKSEL Timer5 clock mux select line 0x4818 03A4 CM_TIMER6_CLKSEL Timer6 clock mux select line 0x4818 03A8 CM_TIMER7_CLKSEL Timer7 clock mux select line 0x4818 03B0 CM_SYSCLK23_CLKSEL SYSCLK23 clock divider value select 0x4818 03B4 CM_SYSCLK24_CLKSEL SYSCLK24 clock divider value select Table 2-11. CM_ACTIVE Register Summary HEX ADDRESS ACRONYM REGISTER NAME 0x4818 0404 CM_HDDSS_CLKSTCTRL HDVPSS clock domain power state transition 0x4818 0408 CM_HDMI_CLKSTCTRL HDMI clock domain power state transition 0x4818 0424 CM_ACTIVE_HDDSS_CLKCTRL HDVPSS clock management control 0x4818 0428 CM_ACTIVE_HDMI_CLKCTRL HDMI clock management control Table 2-12. CM_DEFAULT Register Summary HEX ADDRESS ACRONYM REGISTER NAME 0x4818 0504 CM_DEFAULT_L3_MED_CLKSTCTRL L3 clock domain power state transition 0x4818 0508 CM_DEFAULT_L3_FAST_CLKSTCTRL L3 clock domain power state transition 0x4818 0510 CM_DEFAULT_PCI_CLKSTCTRL PCI clock domain power state transition 0x4818 0514 CM_DEFAULT_L3_SLOW_CLKSTCTRL L3 clock domain power state transition 0x4818 0520 CM_DEFAULT_EMIF_0_CLKCTRL EMIF0 clock management control 0x4818 0524 CM_DEFAULT_EMIF_1_CLKCTRL EMIF1 clock management control 0x4818 0528 CM_DEFAULT_DMM_CLKCTRL DMM clock management control 0x4818 052C CM_DEFAULT_FW_CLKCTRL EMIF FW clock management control 0x4818 0558 CM_DEFAULT_USB_CLKCTRL USB clock management control 0x4818 0560 CM_DEFAULT_SATA_CLKCTRL SATA clock management control 0x4818 0578 CM_DEFAULT_PCI_CLKCTRL PCI clock management control Copyright © 2010–2011, Texas Instruments Incorporated Device Overview 15 Submit Documentation Feedback Product Folder Link(s): AM3894 AM3892 |
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