AM3892 datasheet(20/299 Pages) TI

20 / 299 page

AM3894

AM3892

SPRS681A – OCTOBER 2010 – REVISED MARCH 2011

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Table 2-19. L3 Memory Map (continued)

START ADDRESS

END ADDRESS

QUAD

BLOCK NAME

SIZE

DESCRIPTION

(HEX)

HDMI 1.3 Tx

0x46C0 0000

0x46FF FFFF

4MB

HDMI 1.3 Tx

McBSP

0x4700 0000

0x473F FFFF

4MB

McBSP

USB2.0

0x4740 0000

0x477F FFFF

4MB

USB2.0 Registers / CPPI

Reserved

0x4780 0000

0x47BF FFFF

4MB

Reserved

0x47C0 0000

0x47FF FFFF

4MB

Reserved

L4 Standard domain

0x4800 0000

0x48FF FFFF

16MB

Standard Peripheral domain (see

Table 2-20)

EDMA TPCC

0x4900 0000

0x490F FFFF

1MB

EDMA TPCC Registers

Reserved

0x4910 0000

0x497F FFFF

7MB

Reserved

EDMA TPTC0

0x4980 0000

0x498F FFFF

1MB

EDMA TPTC0 Registers

EDMA TPTC1

0x4990 0000

0x499F FFFF

1MB

EDMA TPTC1 Registers

EDMA TPTC2

0x49A0 0000

0x49AF FFFF

1MB

EDMA TPTC2 Registers

EDMA TPTC3

0x49B0 0000

0x49BF FFFF

1MB

EDMA TPTC3 Registers

Reserved

0x49C0 0000

0x49FF FFFF

4MB

Reserved

L4 High-Speed

0x4A00 0000

0x4AFF FFFF

16MB

High-Speed Peripheral domain (see

Domain

Table 2-21)

Instrumentation

0x4B00 0000

0x4BFF FFFF

16MB

EMU Subsystem region

DDR EMIF0

0x4C00 0000

0x4CFF FFFF

16MB

Configuration registers

registers(1)

DDR EMIF1

0x4D00 0000

0x4DFF FFFF

16MB

Configuration registers

registers(1)

DDR DMM

0x4E00 0000

0x4FFF FFFF

32MB

Configuration registers

Registers(1)

GPMC Registers

0x5000 0000

0x50FF FFFF

16MB

Configuration registers

PCIe Gen2 Registers

0x5100 0000

0x51FF FFFF

16MB

Configuration registers

Reserved

0x5200 0000

0x54FF FFFF

48MB

Reserved

0x5500 0000

0x55FF FFFF

16MB

Reserved

SGX530

0x5600 0000

0x56FF FFFF

16MB

SGX530 Slave Port

AM3894 only)

Reserved

0x5600 0000

0x56FF FFFF

16MB

Reserved

(AM3892 only)

Reserved

0x5700 0000

0x57FF FFFF

16MB

Reserved

0x5800 0000

0x5BFF FFFF

64MB

Reserved

0x5C00 0000

0x5DFF FFFF

32MB

Reserved

0x5E00 0000

0x5FFF FFFF

32MB

Reserved

Tiler

0x6000 0000

0x7FFF FFFF

512MB

Virtual Tiled Address Space

DDR EMIF0/1

0x8000 0000

0xBFFF FFFF

1GB

DDR

SDRAM (2)

DDR EMIF0/1

0xC000 0000

0xFFFF FFFF

1GB

DDR

SDRAM(2)

Q4-7

DDR DMM

0x1 0000 0000

0x1 FFFF FFFF

4GB

DDR DMM Tiler Extended address map –

Virtual Views (HDVPSS only)

(1)

These accesses occur through the DDR DMM Tiler Ports. The DMM will split address ranges internally to address DDR EMIF and DDR

DMM control registers.

(2)

DDR EMIF0 and DDR EMIF1 addresses may be contiguous or bank interleaved depending on configuration of the DDR DMM. See the

DDR DMM documentation for more details.

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