AM3892 datasheet(12/299 Pages) TI

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Mailbox

Interconnect

Interrupt

Mailbox Module

ARM Cortex-A8

Media Controller

AM3894

AM3892

SPRS681A – OCTOBER 2010 – REVISED MARCH 2011

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2.4

Media Controller

The Media Controller has the responsibility of managing the HDVPSS module.

2.5

Inter-Processor Communication

This device is a multi-core device that requires software to efficiently manage and communicate between

the cores. The following are the main features that need to be implemented by such software:

1. Device management of the slave processors from the host processor.

2. Inter-processor communication between the cores for transfer and exchange of information between

them.

For implementing efficient inter-processor communication between the multiple cores on the device, the

following hardware features are provided:

•

Mailbox interrupts

•

Hardware spinlocks

Mailboxes provide a mechanism for one processor to write a value to a register and send an interrupt to

another processor. Spinlocks facilitate access to shared resources in the system.

2.5.1

Mailbox Module

The device Mailbox module facilitates communication between the ARM Cortex-A8 and the Media

Controller. It consists of twelve mailboxes, each supporting communication between two of the above

processors. The sender sends information to the receiver by writing a message to the mailbox registers.

Interrupt signaling is used to notify the receiver that a message has been queued or to notify the sender

about an overflow situation.

The Mailbox module supports the following features (see Figure 2-2):

•

12 mailboxes

•

Four-message FIFO depth for each message queue

•

32-bit message width

•

Message reception and queue-not-full notification using interrupts

•

Three interrupts (one to ARM Cortex-A8, two to Media Controller).

Figure 2-2. Mailbox Module Block Diagram

Device Overview

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