AM3892 datasheet(19/299 Pages) TI

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AM3894

AM3892

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SPRS681A – OCTOBER 2010 – REVISED MARCH 2011

2.8

Memory Map Summary

The device has multiple on-chip memories associated with its processors and various subsystems. To

help simplify software development a unified memory map is used where possible to maintain a consistent

view of device resources across all bus masters.

The device system memory mapping is broken into four 1-GB quadrants for target address spaces

allocation. The four quadrants are labeled Q0, Q1, Q2 and Q3 for a total of 4-GB 32-bit address space.

(HDVPSS includes a thirty-third address bit for an additional 4GB of address range; this is for virtual

addressing and not physical memory addressing.) Inside each quadrant, system targets are mapped on

4-MB boundary (except EDMA targets which are decreased to 1-MB regions).

2.8.1

L3 Memory Map

The L3 high-performance interconnect is based on a Network-on-Chip (NoC) interconnect infrastructure.

The NoC uses an internal packet-based protocol for forward (read command, write command with data

payload) and backward (read response with data payload, write response) transactions. All exposed

interfaces of this NoC interconnect, both for targets and initiators, comply with the OCPIP2.2 reference

standard.

Table 2-19 shows the general device level-3 (L3) memory map. The table represents the physical

addresses used by the L3 infrastructure. Some processors within the device (such as Cortex™-A8 ARM)

may re-map these targets to different virtual addresses through an internal or external MMU. Processors

without MMUs and other bus masters use these physical addresses to access L3 regions. Note that not all

masters have access to all L3 regions, but only those with defined connectivity, as shown in Table 5-1.

For a list of the specific peripherals attached to each of the Level-4 (L4) peripheral ports see Section 5.2.

The L3 interconnect returns an address-hole error if any initiator attempts to access a target to which it

has no connection.

Table 2-19. L3 Memory Map

START ADDRESS

END ADDRESS

QUAD

BLOCK NAME

SIZE

DESCRIPTION

(HEX)

GPMC

0x0000 0000

0x1FFF FFFF

512MB

GPMC

PCIe Gen2

0x2000 0000

0x2FFF FFFF

256MB

PCIe Gen2 Targets

Reserved

0x3000 0000

0x3FFF FFFF

256MB

Reserved

0x4000 0000

0x402F FFFF

3MB

Reserved

L3 OCMC0

0x4030 0000

0x4033 FFFF

256KB

OCMC SRAM

Reserved

0x4034 0000

0x403F FFFF

768KB

Reserved (OCMC RAM0)

L3 OCMC1

0x4040 0000

0x4043 FFFF

256KB

OCMC SRAM

Reserved

0x4044 0000

0x404F FFFF

768KB

Reserved (OCMC RAM1)

Reserved

0x4050 0000

0x407F FFFF

3MB

Reserved

0x4080 0000

0x4083 FFFF

256KB

Reserved

0x4084 0000

0x40DF FFFF

5888KB

Reserved

0x40E0 0000

0x40E0 7FFF

32KB

Reserved

0x40E0 8000

0x40EF FFFF

992KB

Reserved

0x40F0 0000

0x40F0 7FFF

32KB

Reserved

0x40F0 8000

0x40FF FFFF

992KB

Reserved

0x4100 0000

0x41FF FFFF

16MB

Reserved

0x4200 0000

0x43FF FFFF

32MB

Reserved

L3 CFG Regs

0x4400 0000

0x44BF FFFF

12MB

L3 configuration registers

Reserved

0x44C0 0000

0x45FF FFFF

20MB

Reserved

McASP0

0x4600 0000

0x463F FFFF

4MB

McASP0

McASP1

0x4640 0000

0x467F FFFF

4MB

McASP1

McASP2

0x4680 0000

0x46BF FFFF

4MB

McASP2

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