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AM3892 Datasheet(PDF) 48 Page - Texas Instruments |
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AM3892 Datasheet(HTML) 48 Page - Texas Instruments |
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48 / 299 page  AM3894 AM3892 SPRS681A – OCTOBER 2010 – REVISED MARCH 2011 www.ti.com Table 3-3. DDR2/3 Memory Controller 1 Terminal Functions SIGNAL TYPE(1) OTHER(2) DESCRIPTION NAME NO. DDR[1]_CLK[0] B26 O DVDD_DDR[1] DDR[1] Clock 0 DDR[1]_CLK[0] A26 O DVDD_DDR[1] DDR[1] Negative Clock 0 DDR[1]_CLK[1] A23 O DVDD_DDR[1] DDR[1] Clock 1 DDR[1]_CLK[1] B23 O DVDD_DDR[1] DDR[1] Negative Clock 1 DDR[1]_CKE C20 O DVDD_DDR[1] DDR[1] Clock Enable DDR[1]_WE E25 O DVDD_DDR[1] DDR[1] Write Enable DDR[1]_CS[0] B21 O DVDD_DDR[1] DDR[1] Chip Select 0 DDR[1]_CS[1] F20 O DVDD_DDR[1] DDR[1] Chip Select 1 DDR[1]_RAS D25 O DVDD_DDR[1] DDR[1] Row Address Strobe output DDR[1]_CAS C25 O DVDD_DDR[1] DDR[1] Column Address Strobe output DDR[1]_DQM[3] D29 O DVDD_DDR[1] DDR[1] Data Mask outputs DDR[1]_DQM[3]: For upper byte data bus DDR[1]_D[31:24] DDR[1]_DQM[2] G29 O DVDD_DDR[1] DDR[1]_DQM[2]: For DDR[1]_D[23:16] DDR[1]_DQM[1] B33 O DVDD_DDR[1] DDR[1]_DQM[1]: For DDR[1]_D[15:8] DDR[1]_DQM[0]: For lower byte data bus DDR[1]_D[7:0] DDR[1]_DQM[0] C36 O DVDD_DDR[1] DDR[1]_DQS[3] B29 O DVDD_DDR[1] Data strobe input/outputs for each byte of the 32-bit data bus. They are outputs to the DDR[1] memory when writing and inputs when reading. DDR[1]_DQS[2] B30 I/O DVDD_DDR[1] They are used to synchronize the data transfers. DDR[1]_DQS[1] B34 I/O DVDD_DDR[1] DDR[1]_DQS[3]: For upper byte data bus DDR[1]_D[31:24] DDR[1]_DQS[2]: For DDR[1]_D[23:16] DDR[1]_DQS[1]: For DDR[1]_D[15:8] DDR[1]_DQS[0] F34 I/O DVDD_DDR[1] DDR[1]_DQS[0]: For lower byte data bus DDR[1]_D[7:0] DDR[1]_DQS[3] A29 I/O DVDD_DDR[1] Complimentary data strobe input/outputs for each byte of the 32-bit data bus. They are outputs to the DDR[1] memory when writing and DDR[1]_DQS[2] A30 I/O DVDD_DDR[1] inputs when reading. They are used to synchronize the data transfers. DDR[1]_DQS[1] A34 I/O DVDD_DDR[1] DDR[1]_DQS[3]: For upper byte data bus DDR[1]_D[31:24] DDR[1]_DQS[2]: For DDR[1]_D[23:16] DDR[1]_DQS[1]: For DDR[1]_D[15:8] DDR[1]_DQS[0] E35 I/O DVDD_DDR[1] DDR[1]_DQS[0]: For lower byte data bus DDR[1]_D[7:0] DDR[1]_ODT[0] E20 O DVDD_DDR[1] DDR[1] On-Die Termination for Chip Select 0. DDR[1]_ODT[1] A22 O DVDD_DDR[1] DDR[1] On-Die Termination for Chip Select 1. DDR[1]_RST D20 O DVDD_DDR[1] DDR[1] Reset output DDR[1]_BA[2] N23 O DVDD_DDR[1] DDR[1]_BA[1] B24 O DVDD_DDR[1] DDR[1] Bank Address outputs DDR[1]_BA[0] F25 O DVDD_DDR[1] (1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal. (2) Specifies the operating I/O supply voltage for each signal. 48 Device Pins Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM3894 AM3892 |
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