TDA8296 datasheet(47/87 Pages) NXP

47 / 87 page

TDA8296

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Product data sheet

Rev. 1 — 3 March 2011

47 of 87

NXP Semiconductors

TDA8296

Digital global standard low IF demodulator for analog TV and FM radio

For optimum performances, the following relations must be respected:

• 275 MHz ≤ fVCO ≤ 550 MHz

• 4 kHz ≤ fi / N ≤ 150 MHz

9.3.18 GPIOs

In the TDA8296, three general purpose input/outputs are implemented.

Table 54.

GPIOREG_0 register (address 44h) bit description

Legend: * = default value.

Bit

Symbol

Access Value

Description

7 to 4 GP1_CF[3:0]

R/W

It determines how the general purpose pin GPIO1 is

configured.

0000

The GPIO1 pin is in Input mode. The input value is

stored in GP1_VAL.

0001*

The GPIO1 pin is in Open-drain mode. The output

value is determined by GP1_VAL.

0011

The GPIO1 pin is in Output mode. The PLL output

clock divided by two is delivered.

0100

1011

The GPIO1 pin is in Output mode. HVPLL signals are

delivered. The HVPLL signal is chosen according to

Table 56.

XXXX

Don’t care if I2CSW_EN = 1. Then the pad is

configured as I2C-bus feed-through like described in

Table 55.

3 to 0 GP0_CF[3:0]

R/W

It determines how the general purpose pin GPIO0 is

configured.

0000

The GPIO0 pin is in Input mode. The input value is

stored in GP0_VAL.

0001

The GPIO0 pin is in Open-drain mode. The output

value is determined by GP0_VAL.

0011

The GPIO0 pin is in Output mode. The PLL output

clock divided by two is delivered.

0100

1011*

The GPIO0 pin is in Output mode. HVPLL signals are

delivered. The HVPLL signal is chosen according to

Table 56.

Table 55.

GPIOREG_1 register (address 45h) bit description

Legend: * = default value.

Bit

Symbol

Access Value

Description

I2CSW_EN

R/W

When I2CSW_EN = 1, GPIO1 and GPIO2 are

configured as an I2C-bus feed-through independently of

the GP1_CF and GP2_CF value. When

I2CSW_ON = 0, the feed-through switch is open, and

GPIO1 and GPIO2 are in 3-state. When the switch is

closed (I2CSW_ON = 1), the I2C-bus clock and data

signals (SCL and SDA) are available on the GPIO1 and

GPIO2 pins.

I2CSW_ON

R/W

5 and 4 -

R/W

00*

not used

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