TDA8296 datasheet(9/87 Pages) NXP

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TDA8296

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Product data sheet

Rev. 1 — 3 March 2011

9 of 87

NXP Semiconductors

TDA8296

Digital global standard low IF demodulator for analog TV and FM radio

[1]

The pin types are defined in Table 5.

Boundary scan

TMS

Test mode select provides the logic levels needed to change the TAP controller from

state to state during the boundary scan test.

TRST_N

Test reset is used to reset the TAP controller (active LOW). Grounding is mandatory

in Functional mode.

TCK

Test clock is used to drive the TAP controller.

TDI

Test data input is the serial data input for the test data instruction.

TDO

Test data output is the serial test data output pin. The data is provided on the falling

edge of TCK.

ADC

IF_POS

IF positive analog input for internal ADC

IF_NEG

IF negative analog input for internal ADC

DAC

V_IOUTP

positive analog current output of the video output

V_IOUTN

negative analog current output of the video output

S_IOUTP

positive analog current output of the SSIF/mono sound output

S_IOUTN

negative analog current output of the SSIF/mono sound output

RSET

External bias setting of the DACs. An external resistor (1 k

Ω typical) has to be

connected between RSET and the analog ground of the board. This resistor

generates the current into the DACs and also defines the full scale output current.

The total parasitic capacitance seen externally from the RSET pin has to be lower

than 20 pF.

Supplies and grounds

VDDA(DAC1)(3V3) 15

DAC1 (video DAC) and DAC reference module analog supply voltage (3.3 V typical)

VDDA(DAC2)(3V3) 18

DAC2 (sound DAC) analog supply voltage (3.3 V typical)

VSSA(DAC)

GND

DAC reference module analog ground supply voltage (0 V typical)

VDDA(ADC)(1V2)

IF ADC analog supply voltage (1.2 V typical)

VSSA(ADC)

GND

ADC analog ground supply voltage (0 V typical)

VDDD1(1V2)

ADC, PLL and DACs digital supply voltage (1.2 V typical)

VSSD1

GND

ADC, PLL and DACs digital ground supply voltage (0 V typical)

VDDA(PLL)(1V2)

crystal oscillator and clock PLL analog supply voltage (1.2 V typical)

VSSA(PLL)

GND

crystal oscillator and clock PLL analog ground supply voltage (0 V typical)

VDDD2(1V2)

core digital supply voltage (1.2 V typical)

VSSD2

GND

core digital ground supply voltage (0 V typical)

VDDDR(3V3)

ring digital supply voltage (3.3 V typical)

VSSDR

GND

ring digital ground supply voltage (0 V typical)

VSS

die pad

GND

Other pins

i.c.

6, 36,

internally connected; connect to ground

n.c.

not connected

Table 4.

Pin description …continued

Symbol

Type[1]

Description

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