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TAS5548 Datasheet(PDF) 46 Page - Texas Instruments

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Part # TAS5548
Description  8-Channel HD Compatible Audio Processor with ASRC and PWM Output
PDF  120 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TAS5548 Datasheet(HTML) 46 Page - Texas Instruments

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TAS5548
SLES270 – NOVEMBER 2012
www.ti.com
6.2
Programming Energy Manager
Energy Manager related registers are 0xBA to 0xBE. 0xB2 is a 16 byte averaging filter (alpha filter) for
both satellite and sub channel. The scaling coefficients are 0xB3 to 0xBA that multiplies energy of each
channel with a scaling factor. The threshold registers are (0xBB, 0xBC, 0xBD and 0xBE) and 0x10 for the
results register.
Table 6-1. Energy Manager Status Register (x10)
D3
D2
D1
D0
FUNCTION
–
–
–
0/1
Energy below the low threshold for satellite channels
–
–
0/1
–
Energy above the high threshold for satellite channels
–
0/1
–
–
Energy below the low threshold for sub-woofer
channel
0/1
–
–
–
Energy above the high threshold for sub-woofer
channels
So provision to read the whole byte and a way to clear the 4 LSB’s (one by one)
6.3
AM Avoidance Strategies
6.3.1
Frequency Scaling AM Avoidance
The AM avoidance strategy exploits the presence of the ASRC. The APLL output frequency is directly
varied by varying the multiplier ratio in the PLL loop. The dividers to generate clocks from the APLL are
fixed at their nominal division factor, so the result is that the internal sampling rate is changing accordingly.
The ASRC will adapt with this changing output rate (the internal sampling rate) and convert the incoming
sampling rates to this rate accordingly. The rest of the circuit does not change and operates normally, but
since the APLL output frequency is varied while the clock dividers are fixed, the PWM carrier frequency
becomes varied also, which is the goal of this AM avoidance strategy.
This shift in processing rate will effect time-domain digital processing, such as the EQ's and DRC's decay
values by the value in Freq_Error below.
Table 6-2. APLL/DAP/ASRC Clock Frequencies with New AM Avoidance Strategy
Input
Prescal
Feedba
Internal
# cycles
ASRC
Freq_Erro
Mode
XTAL
DCLK
DAP CLK
PWM rate
FS
e
ck
SR
per FS
CLK
r
Normal
8 - 192k
12288
4
64
196608
96
131072
1365.33
98304
384
0.00%
AM#1
8 - 192k
12288
4
62
190464
93
126976
1365.33
95232
372
-3.13%
AM#2
8 - 192k
12288
4
60
184320
90
12288
1365.33
92160
360
-6.25%
AM#3
8 - 192k
12288
4
58
178176
87
118784
1365.33
89088
348
-9.38%
AM#4
8 - 192k
12288
4
56
172032
84
114688
1365.33
86016
336
-12.50%
46
System Power Controller
Copyright © 2012, Texas Instruments Incorporated
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