TAS5548 datasheet(6/120 Pages) TI

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TAS5548

SLES270 – NOVEMBER 2012

www.ti.com

TERMINAL

5-V

TYPE(1)

TERMINATION(2)

DESCRIPTION

TOLERANT

NAME

NO.

RESET

5 V

Pullup

System reset input, active-low. A system reset is generated by applying a logic

low to this terminal. RESET is an asynchronous control signal that restores the

TAS5548 to its default conditions, sets the valid output low, and places the

PWM in the hard-mute state (Non PWM Switching). Master volume is

immediately set to full attenuation. On the release of RESET, if PDN is high, the

system performs a 4- to 5-ms device initialization and sets the volume at mute.

SCL

5 V

I2C serial-control clock input/output

SCLK

5 V

Pulldown(2)

Serial-audio data clock (shift clock) input

SDA

DIO

5 V

I2C serial-control data-interface input/output

SDIN1

5 V

Pulldown

Serial-audio data bank 1 input 1 is one of the serial-data input ports and goes

into the 1st SRC Bank. Four discrete (stereo) data formats and is capable of

inputting data at 64 fS.

SDIN1

5 V

Pulldown

Serial-audio data bank 1 input 2 is one of the serial-data input ports and goes

into the 1st SRC Bank. Four discrete (stereo) data formats and is capable of

inputting data at 64 fS.

SDIN2-1

5 V

Pulldown

Serial-audio data bank 2 input 1 is one of the serial-data input ports and goes

into the 2nd SRC Bank. Four discrete (stereo) data formats and is capable of

inputting data at 64 fS.

SDIN2-2

5 V

Pulldown

Serial-audio data bank 2 input 2 is one of the serial-data input ports and goes

into the 2nd SRC Bank. Four discrete (stereo) data formats and is capable of

inputting data at 64 fS.

VALID

Output indicating validity of PWM outputs, active-high

VR_DIG

Voltage reference for 1.8-V digital core supply. A pinout of the internally

regulated 1.8-V power used by digital core logic. A 4.7-

μF low-ESR capacitor(3)

should be connected between this terminal and DVSS. This terminal must not

be used to power external devices.

VR_PWM

Voltage reference for 1.8-V digital PLL supply. A pinout of the internally

regulated 1.8-V power used by digital PLL logic. A 0.1-

μF low-ESR capacitor(3)

should be connected between this terminal and DVSS_CORE. This terminal

must not be used to power external devices.

ASEL_EMO2

DIO

Pullup

I2C Address Select. Address will 0X34/0X36 with the value of pin being "0' or

"1" during de-assertion of reset. Can be programmed to be an output (as energy

manager output for subwoofer)

AVDD

Analog supply (3.3 V) for PLL.

EMO1

Energy Manger Output interrupt - Asserted high when threshold is exceeded.

LRCLKO /

DIO

Pulldown

LRCLK for I2S OUT. Can also be used as LRCKIN_2 (I2S Input for SDIN2_x

LRCKIN_2

and SRC Bank 2)

SDOUT / SDIN5

I2S data out or SDIN5 (must be sync'd to post SRC rate). Usually used for

Microphone ADC Input

SCLKO /

DIO

Pulldown

Serial data clock out. I2S bit clock out. Can also be used as SCLKIN_2 (I2S

SCLKIN_2

Input for SDIN2_x and SRC Bank 2)

TEST

Test mode active high. In normal mode tie this to digital ground.

VR_ANA

(3)

If desired, low-ESR capacitance values can be implemented by paralleling two or more ceramic capacitors of equal value. Paralleling

capacitors of equal value provides an extended high-frequency supply decoupling. This approach avoids the potential of producing

parallel resonance circuits that have been observed when paralleling capacitors of different values.

2.2

ORDERING INFORMATION

Orderable Device

Package

Pins

MSL

TAS5548DCA

DCA

LEVEL3-260C

TAS5548DCAR

DCA

LEVEL3-260C

Description

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