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TAS5548 Datasheet(PDF) 5 Page - Texas Instruments

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Part # TAS5548
Description  8-Channel HD Compatible Audio Processor with ASRC and PWM Output
PDF  120 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

TAS5548 Datasheet(HTML) 5 Page - Texas Instruments

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TAS5548
www.ti.com
SLES270 – NOVEMBER 2012
2.1.2
Terminal Descriptions
TERMINAL
5-V
TYPE(1)
TERMINATION(2)
DESCRIPTION
TOLERANT
NAME
NO.
AVDD_PWM
50
P
3.3-V analog power supply for PWM. This terminal can be connected to the
same power source used to drive power terminal DVDD; but to achieve low PLL
jitter, this terminal should be bypassed to AVSS_PWM with a 0.1-
μF low-ESR
capacitor.
AVSS
5
P
Analog ground
AVSS_PWM
51
P
Analog ground for PWM. Must have direct return Cu path to analog 3.3V supply
for optimized performance.
BKND_ERR
34
DI
Pullup(2)
Active-low. A back-end error sequence is generated by applying logic low to this
terminal. The BKND_ERR results in no change to I2C parameters, with all H-
bridge drive signals going to a hard-mute state (Non PWM Switching).
DVDD1
35
P
3.3-V digital power supply. (It is recommended that decoupling capacitors of
0.1
μF and 10 μF be mounted close to this pin).
DVDD2
14
P
3.3-V digital power supply for PWM. (It is recommended that decoupling
capacitors of 0.1
μF and 10 μF be mounted close to this pin).
DVSS1
36
P
Digital ground 1
DVSS2
13
P
Digital ground 2
HP_SEL
17
DI
5 V
Pullup(2)
Headphone/speaker selector. When a logic low is applied, the headphone is
selected (speakers are off). When a logic high is applied, speakers are selected
(headphone is off).
LRCLK
22
DI
5 V
Pulldown(2)
Serial-audio data left/right clock (sampling-rate clock)
XTALI
11
DI
1.8 V
XTAL input. Connect to external 12.288 MHz XTAL
MUTE
19
DI
5 V
Pullup(2)
Soft mute of outputs, active-low (muted signal = a logic low, normal operation =
a logic high). The mute control provides a noiseless volume ramp to silence.
Releasing mute provides a noiseless ramp to previous volume.
XTALO
12
DO
XTAL input. Connect to external 12.288 MHz XTAL
PDN
18
DI
5 V
Pullup(2)
Power down, active-low. PDN powers down all logic and stops all clocks
whenever a logic low is applied. The I2C parameters are preserved through a
power-down cycle, as long as RESET is not active.
PLL_FLTM
6
AIO
PLL negative filter.
PLL_FLTP
7
AIO
PLL positive filter.
PSVC/MCLKO
33
DO
Power-supply volume control PWM output or MCKO for external ADC (SDIN5
Source)
PWM_HPM_L
1
DO
PWM left-channel headphone (differential –)
PWM_HPM_R
3
DO
PWM right-channel headphone (differential –)
PWM_HPP_L
2
DO
PWM left-channel headphone (differential +)
PWM_HPP_R
4
DO
PWM right-channel headphone (differential +)
PWM_M_1
38
DO
PWM 1 output (differential –)
PWM_M_2
40
DO
PWM 2 output (differential –)
PWM_M_3
42
DO
PWM 3 output (differential –)
PWM_M_4
44
DO
PWM 4 output (differential –)
PWM_M_5
53
DO
PWM 5 output (lineout L) (differential –)
PWM_M_6
55
DO
PWM 6 output (lineout R) (differential –)
PWM_M_7
46
DO
PWM 7 output (differential –)
PWM_M_8
48
DO
PWM 8 output (differential –)
PWM_P_1
39
DO
PWM 1 output (differential +)
PWM_P_2
41
DO
PWM 2 output (differential +)
PWM_P_3
43
DO
PWM 3 output (differential +)
PWM_P_4
45
DO
PWM 4 output (differential +)
PWM_P_5
54
DO
PWM 5 output (lineout L) (differential +)
PWM_P_6
56
DO
PWM 6 output (lineout R) (differential +)
PWM_P_7
47
DO
PWM 7 output (differential +)
PWM_P_8
49
DO
PWM 8 output (differential +)
(1)
Type: A = analog; D = 3.3-V digital; P = power/ground/decoupling; I = input; O = output
(2)
All pullups are 20-
μA weak pullups and all pulldowns are 20-μA weak pulldowns. The pullups and pulldowns are included to ensure
proper input logic levels if the terminals are left unconnected (pullups
→ logic-1 input; pulldowns → logic-0 input). Devices that drive
inputs with pullups must be able to sink 20
μA while maintaining a logic-0 drive level. Devices that drive inputs with pulldowns must be
able to source 20
μA while maintaining a logic-1 drive level.
Copyright © 2012, Texas Instruments Incorporated
Description
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