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TAS5548 Datasheet(PDF) 26 Page - Texas Instruments |
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TAS5548 Datasheet(HTML) 26 Page - Texas Instruments |
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26 / 120 page  7 Biquads in Series Bass and Treble DRC Bass and Treble Bypass Bass and Treble Inline Pre- Volume Post- Volume DRC Bypass DRC Inline B0016-02 From Input Mixer To Output Mixer Loudness Channel Volume Master Volume Max Volume TAS5548 SLES270 – NOVEMBER 2012 www.ti.com All of the TAS5548 default values for DRC can be used except for the DRC1 decay and DRC2 decay. Table 3-5 shows the recommended time constants and their hex values. If the user wants to implement other DRC functions, Texas Instruments recommends using the GUI available from Texas Instruments. The tool allows the user to select the DRC transfer function graphically. It then outputs the TAS5548 hex coefficients for download to the TAS5548. Table 3-5. DRC Recommended Changes From TAS5548 Defaults I2C RECOMMENDED RECOMMENDED DEFAULT TIME SUBADDRESS REGISTER FIELDS TIME HEX VALUE DEFAULT HEX CONSTANT (ms) CONSTANT (ms) 0x98 DRC1 energy 5 0000 883F 0000 883F DRC1 (1 – energy) 007F 77C0 007F 77C0 0x9C DRC1 attack 5 0000 883F 0000 883F DRC1 (1 – attack) 007F 77C0 007F 77C0 DRC1 decay 2 0001 538F 0000 0056 DRC1 (1 – decay) 007E AC70 003F FFA8 0x9D DRC2 energy 5 0000 883F 0000 883F DRC2 (1 – energy) 007F 77C0 007F 77C0 0xA1 DRC2 attack 5 0000 883F 0000 883F DRC2 (1 – attack) 007F 77C0 007F 77C0 DRC2 decay 2 0001 538F 0000 0056 DRC2 (1 – decay) 007E AC70 003F FFA8 Recommended DRC setup flow if the defaults are used: • After power up, load the recommended hex value for DRC1 and DRC2 decay and (1 – decay). See Table 3-5. • Enable either the pre-volume or post-volume DRC using I2C registers 0x96 and 0x97. Note that to avoid a potential timing problem, there is a 10-ms delay between a write to 0x96 and a write to 0x97. Recommended DRC setup flow if the DRC design uses values different from the defaults: • After power up, load all DRC coefficients per the DRC design. • Enable either the pre-volume or post-volume DRC. Note that to avoid a potential timing problem, there is a 10-ms delay between a write to 0x96 and a write to 0x97. Figure 3-15 shows the positioning of the DRC block in the TAS5548 processing flow. As seen, the DRC input can come either before or after soft volume control and loudness processing. Figure 3-15. DRC Positioning in TAS5548 Processing Flow 26 TAS5548 DAP Architecture Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TAS5548 |
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