TAS5548 datasheet(16/120 Pages) TI

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Digital Audio Processor Core

IN 1

COEF

RAM

Data

RAM

Code

ROM

Controller

8052

MCU

(8-Bit)

External

Data

RAM

Internal

Data

RAM

Code

ROM

SCL

SDA

CS 0

IN 2

IN 4

IN 3

Memory

Interface

T/B

Control

Registers

I2C

Serial

Interface

Data

Path

Micro Core

PWM

IN 5

OUT 2

IN7

IN6

IN 8

IN9

IN10

OUT 1

TAS5548

SLES270 – NOVEMBER 2012

www.ti.com

3.2

2C Coefficient Number Formats

The architecture of the TAS5548 is contained in ROM resources within the device and cannot be altered.

However, mixer gain, level offset, and filter tap coefficients, which can be entered via the I2C bus interface,

provide a user with the flexibility to set the TAS5548 to a configuration that achieves system-level goals.

The firmware is executed in a 32-bit, signed, fixed-point arithmetic machine. The most significant bit of the

32-bit data path is a sign bit, and the 31 lower bits are data bits. Mixer gain operations are implemented

by multiplying a 32-bit, signed data value by a 28-bit, signed gain coefficient (known as 5.23 in the rest of

this document. See for more details). The 60-bit, signed output product is then truncated to a signed, 32-

bit number. Level offset operations are implemented by adding a 32-bit, signed offset coefficient to a 32-

bit, signed data value.

In most cases, if the addition results in overflowing the 32-bit, signed number format, saturation logic is

used. This means that if the summation results in a positive number that is greater than 0x7FFF FFFF FF

(the spaces are used to ease the reading of the hexadecimal number), the number is set to

0x7FFF FFFF FF. If the summation results in a negative number that is less than 0x8000 0000 00, the

number is set to 0x8000 0000 00. This allows the system to clip in a similar way to an analog circuit, rather

than "wrapping around" to a polar opposite output.

Figure 3-4. DAP Block Diagram

TAS5548 DAP Architecture

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