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TAS5548 Datasheet(PDF) 14 Page - Texas Instruments |
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TAS5548 Datasheet(HTML) 14 Page - Texas Instruments |
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14 / 120 page  IP Mixer 1 (I2C 0x41 ) 10 X 8 Crossbar Input Mixer A H G F E D C B I J SDIN1-L (L) (1) SDIN1-R (R) SDIN2-L (LS) SDIN2-R (RS) SDIN3-L (LBS) SDIN3-R (RBS) SDIN4-L (C) SDIN4-R (LFE) MIC-L-IN MIC-R-IN IP Mixer 2 (I2C 0x42 ) 10 X 8 Crossbar Input Mixer A H G F E D C B I J SDIN1-L (L) SDIN1-R (R) (1) SDIN2-L (LS) SDIN2-R (RS) SDIN3-L (LBS) SDIN3-R (RBS) SDIN4-L (C) SDIN4-R (LFE) MIC-L-IN MIC-R-IN IP Mixer 3 (I2C 0x43 ) 10 X 8 Crossbar Input Mixer A H G F E D C B I J SDIN1-L (L) SDIN1-R (R) SDIN2-L (LS) (1) SDIN2-R (RS) SDIN3-L (LBS) SDIN3-R (RBS) SDIN4-L (C) SDIN4-R (LFE) MIC-L-IN MIC-R-IN IP Mixer 4 (I2C 0x44 ) 10 X 8 Crossbar Input Mixer A H G F E D C B I J SDIN1-L (L) SDIN1-R (R) SDIN2-L (LS) SDIN2-R (RS) (1) SDIN3-L (LBS) SDIN3-R (RBS) SDIN4-L (C) SDIN4-R (LFE) MIC-L-IN MIC-R-IN IP Mixer 5 (I2C 0x45 ) 10 X 8 Crossbar Input Mixer A H G F E D C B I J SDIN1-L (L) SDIN1-R (R) SDIN2-L (LS) SDIN2-R (RS) SDIN3-L (LBS) (1) SDIN3-R (RBS) SDIN4-L (C) SDIN4-R (LFE) MIC-L-IN MIC-R-IN IP Mixer 6 (I2C 0x46 ) 10 X 8 Crossbar Input Mixer A H G F E D C B I J SDIN1-L (L) SDIN1-R (R) SDIN2-L (LS) SDIN2-R (RS) SDIN3-L (LBS) SDIN3-R (RBS) (1) SDIN4-L (C) SDIN4-R (LFE) MIC-L-IN MIC-R-IN IP Mixer 7 (I2C 0x47 ) 10 X 8 Crossbar Input Mixer A H G F E D C B I J SDIN1-L (L) SDIN1-R (R) SDIN2-L (LS) SDIN2-R (RS) SDIN3-L (LBS) SDIN3-R (RBS) SDIN4-L (C) (1) SDIN4-R (LFE) MIC-L-IN MIC-R-IN IP Mixer 8 (I2C 0x48 ) 10 X 8 Crossbar Input Mixer A H G F E D C B I J SDIN1-L (L) SDIN1-R (R) SDIN2-L (LS) SDIN2-R (RS) SDIN3-L (LBS) SDIN3-R (RBS) SDIN4-L (C) SDIN4-R (LFE) (1) MIC-L-IN MIC-R-IN 2 DAP 7 BQ (0x82 - 0x83 2 DAP 7 BQ (0x7B- 0x7C Coeff =0 (lin), (I2C 0xXX) Coeff=0 (lin), (I2C 0x4C) Coeff=1 (lin), (I2C 0x50 ) Coeff=1 (lin), (I2C 0x4D ) Coeff =0 (lin), (I2C 0x4B) Coeff=0 (lin), (I2C 0x4E ) Coeff =0 (lin), (I2C 0x4A) Coeff=0 (lin), (I2C 0x49 ) 7 DAP 1 BQ (0x51 - 0x57 7 DAP 2 BQ (0x58 - 0x5E 7 DAP 3 BQ (0x5F - 0x65 7 DAP 4 BQ (0x66 - 0x6C 7 DAP 5 BQ (0x6D- 0x73 7 DAP 6 BQ (0x74 - 0x7A 5 DAP 7 BQ (0x7D- 0x81 5 DAP 8 BQ (0x84 - 0x88 Bass Treble 1 BQ (0xDA- 0xDD Bass Treble 2 BQ (0xDA- 0xDD Bass Treble 3 BQ (0xDA- 0xDD Bass Treble 4 BQ (0xDA- 0xDD Bass Treble 5 BQ (0xDA- 0xDD Bass Treble 6 BQ (0xDA- 0xDD Bass Treble 7 BQ (0xDA- 0xDD Bass Treble 8 BQ (0xDA- 0xDD Volume 1 0xD1 Volume 2 0xD2 Volume 3 0xD3 Loudnes s 1 (0x91 - 0x95 OP Mixer 1 (I2C 0xAA) 8 × 2 Output Mixer Volume 4 0xD4 Volume 5 0xD5 Volume 6 0xD6 Volume 7 0xD7 Volume 8 0xD8 Loudnes s 2 (0x91 - 0x95 Loudnes s 3 (0x91 - 0x95 Loudnes s 4 (0x91 - 0x95 Loudnes s 5 (0x91 - 0x95 Loudnes s 6 (0x91 - 0x95 Loudnes s 7 (0x91 - 0x95 Loudnes s 8 (0x91 - 0x95 DRC 1 (0x96 - 0x9C DRC 1 (0x96 - 0x9C DRC 1 (0x96 - 0x9C DRC 1 (0x96 - 0x9C DRC 1 (0x96 - 0x9C DRC 1 (0x9D- 0xA1 DRC 1 (0xXX- 0xXX DRC 2 (0xXX- 0xXX OP Mixer 2 (I2C 0xAB) 8 × 2 Output Mixer OP Mixer 3 (I2C 0xAC) 8 × 2 Output Mixer OP Mixer 4 (I2C 0xAD) 8 × 2 Output Mixer OP Mixer 5 (I2C 0xAE) 8 × 2 Output Mixer OP Mixer 6 (I2C 0xAF) 8 × 2 Output Mixer OP Mixer 7 (I2C 0xB0) 8 × 3 Output Mixer OP Mixer 8 (I2C 0xB1) 8 × 3 Output Mixer Master Vol (0xD9) Max VOL THD Management xE9, xEA L to PWM1 R to PWM2 LS to PWM3 RS to PWM4 LBS to PWM5 RBS to PWM6 C to PWM7 Sub to PWM8 TAS5548 SLES270 – NOVEMBER 2012 www.ti.com 3 TAS5548 DAP Architecture 3.1 TAS5548 DAP Architecture Diagrams The TAS5548 defaults to processing audio data (post ASRC) at double rate. In the TAS5548, this is set to 96kHz (by the external XTAL used). . Additional support is provided for native 192kHz support. 4ch of audio processing is available in 192kHz native processing mode. Figure 3-1 shows the TAS5548 DAP architecture for fS ≤ 96 kHz. The bass management architecture is shown in channels 1, 2, 7 and 8. The I2C registers are shown to help the designer configure the device. Figure 3-2 shows the architecture for fS = 176.4 kHz or fS = 192 kHz. Note that only channels 1, 2, and 8 contain all the features. Channels 3–7 are pass-through except for volume controls. Figure 3-3 shows TAS5548 detailed channel processing. The output mixer is 8×2 for channels 1–6 and 8×3 for channels 7 and 8. (1) Default inputs Figure 3-1. TAS5548 DAP Architecture With I2C Registers (fS ≤ 96 kHz) 14 TAS5548 DAP Architecture Copyright © 2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TAS5548 |
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